220.127.116.11. TX Core FIFO
The TX Core FIFO provides an interface between the FPGA Fabric and across the EMIB to the TX PCS FIFO. It ensures reliable transfer of the data and status signals.
- Phase Compensation Mode
- Register Mode
- Interlaken Mode
- Basic Mode
Phase Compensation Mode
In Phase Compensation mode, the TX Core FIFO decouples phase variations between tx_coreclkin and PCS_clkout_x2(tx). In this mode, the read and write controls of the TX Core FIFO, can be driven by clocks from asynchronous clock sources but must be the same frequency with 0 ppm difference. You can use the FPGA fabric clock or tx_clkout (TX parallel clock) to clock the write side of the TX Core FIFO.
The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with its write clock. In Register Mode, tx_parallel_data (data), tx_control (indicates whether tx_parallel_data is a data or control word), and tx_enh_data_valid (data valid) are registered at the FIFO output. The FIFO in Register Mode has one register stage or one parallel clock latency.
In Interlaken mode, the TX Core FIFO operates as an elastic buffer. In this mode, you have additional signals to control the data flow into the FIFO. Therefore, the FIFO write clock frequency does not have to be the same as the read clock frequency. You can control the writing to the TX Core FIFO with tx_fifo_wr_en by monitoring the FIFO flags. The goal is to prevent the FIFO from becoming full or empty. On the read side, read enable is controlled by the Interlaken frame generator.
In Basic mode, the TX FIFO operates as an elastic buffer, where buffer depths can vary. This mode allows driving write and read side of TX Core FIFO with different clock frequencies. Monitor the FIFO flag to control write and read operations. For TX Core FIFO, assert tx_fifo_wr_en signal with tx_fifo_pempty signal going low.
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