L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.7. Enhanced PCS Parameters

This section defines parameters available in the Native PHY IP core GUI to customize the individual blocks in the Enhanced PCS.

The following tables describe the available parameters. Based on the selection of the Transceiver Configuration Rule , if the specified settings violate the protocol standard, the Native PHY IP core Parameter Editor prints error or warning messages.

Note: For detailed descriptions about the optional ports that you can enable or disable, refer to the Enhanced PCS Ports section.
Table 26.  Enhanced PCS Parameters
Parameter Range Description
Enhanced PCS / PMA interface width 32, 40, 64 Specifies the interface width between the Enhanced PCS and the PMA.
FPGA fabric /Enhanced PCS interface width 32, 40, 64, 66, 67 Specifies the interface width between the Enhanced PCS and the FPGA fabric.

The 66-bit FPGA fabric to PCS interface width uses 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 66-bit word, with lower 2 bits from the control bus.

The 67-bit FPGA fabric to PCS interface width uses the 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 67-bit word with lower 3 bits from the control bus.

Enable 'Enhanced PCS' low latency mode On/Off Enables the low latency path for the Enhanced PCS. When you turn on this option, the individual functional blocks within the Enhanced PCS are bypassed to provide the lowest latency path from the PMA through the Enhanced PCS. When enabled, this mode is applicable for GX transceiver channels. Intel recommends not enabling it for GXT transceiver channels..
Table 27.  Interlaken Frame Generator Parameters
Parameter Range Description
Enable Interlaken frame generator On / Off Enables the frame generator block of the Enhanced PCS.
Frame generator metaframe length 5-8192 Specifies the metaframe length of the frame generator. This metaframe length includes 4 framing control words created by the frame generator.
Enable Frame Generator Burst Control On / Off Enables frame generator burst. This determines whether the frame generator reads data from the TX FIFO based on the input of port tx_enh_frame_burst_en.
Enable tx_enh_frame port On / Off Enables the tx_enh_frame status output port. When the Interlaken frame generator is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.
Enable tx_enh_frame_diag_status port On / Off Enables the tx_enh_frame_diag_status 2‑bit input port. When the Interlaken frame generator is enabled, the value of this signal contains the status message from the framing layer diagnostic word. This signal is synchronous to tx_clkout.
Enable tx_enh_frame_burst_en port On / Off Enables the tx_enh_frame_burst_en input port. When burst control is enabled for the Interlaken frame generator, this signal is asserted to control the frame generator data reads from the TX FIFO. This signal is synchronous to tx_clkout.
Table 28.  Interlaken Frame Synchronizer Parameters
Parameter Range Description
Enable Interlaken frame synchronizer On / Off When you turn on this option, the Enhanced PCS frame synchronizer is enabled.
Frame synchronizer metaframe length 5-8192 Specifies the metaframe length of the frame synchronizer.
Enable rx_enh_frame port On / Off Enables the rx_enh_frame status output port. When the Interlaken frame synchronizer is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.
Enable rx_enh_frame_lock port On / Off Enables the rx_enh_frame_lock output port. When the Interlaken frame synchronizer is enabled, this signal is asserted to indicate that the frame synchronizer has achieved metaframe delineation. This is an asynchronous output signal.
Enable rx_enh_frame_diag_status port On / Off Enables therx_enh_frame_diag_status output port. When the Interlaken frame synchronizer is enabled, this signal contains the value of the framing layer diagnostic word (bits [33:32]). This is a 2 bit per lane output signal. It is latched when a valid diagnostic word is received. This is an asynchronous signal.
Table 29.  Interlaken CRC32 Generator and Checker Parameters
Parameter Range Description
Enable Interlaken TX CRC-32 Generator On / Off When you turn on this option, the TX Enhanced PCS datapath enables the CRC32 generator function. CRC32 can be used as a diagnostic tool. The CRC contains the entire metaframe including the diagnostic word.
Enable Interlaken TX CRC-32 generator error insertion On / Off When you turn on this option, the error insertion of the interlaken CRC-32 generator is enabled. Error insertion is cycle-accurate. When this feature is enabled, the assertion of tx_control[8] or tx_err_ins signal causes the CRC calculation during that word is incorrectly inverted, and thus, the CRC created for that metaframe is incorrect.
Enable Interlaken RX CRC-32 checker On / Off Enables the CRC-32 checker function.
Enable rx_enh_crc32_err port On / Off When you turn on this option, the Enhanced PCS enables the rx_enh_crc32_err port. This signal is asserted to indicate that the CRC checker has found an error in the current metaframe. This is an asynchronous signal.
Table 30.  10GBASE-R BER Checker Parameters
Parameter Range Description
Enable rx_enh_highber port (10GBASE‑R) On / Off Enables the rx_enh_highber port. For 10GBASE-R transceiver configuration rule, this signal is asserted to indicate a bit error rate higher than 10 -4 . Per the 10GBASE-R specification, this occurs when there are at least 16 errors within 125 μs. This is an asynchronous signal.
Enable rx_enh_highber_clr_cnt port (10GBASE‑R) On / Off Enables the rx_enh_highber_clr_cnt input port. For the 10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of times the BER state machine has entered the "BER_BAD_SH" state. This is an asynchronous signal.
Enable rx_enh_clr_errblk_count port (10GBASE‑R&FEC) On / Off Enables the rx_enh_clr_errblk_count input port. For the 10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of the times the RX state machine has entered the RX_E state. For protocols with FEC block enabled, this signal is asserted to reset the status counters within the RX FEC block. This is an asynchronous signal.
Table 31.  64b/66b Encoder and Decoder Parameters
Parameter Range Description
Enable TX 64b/66b encoder (10GBASE-R) On / Off When you turn on this option, the Enhanced PCS enables the TX 64b/66b encoder.
Enable RX 64b/66b decoder (10GBASE-R) On / Off When you turn on this option, the Enhanced PCS enables the RX 64b/66b decoder.
Enable TX sync header error insertion On / Off When you turn on this option, the Enhanced PCS supports cycle-accurate error creation to assist in exercising error condition testing on the receiver. When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly. If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
Table 32.  Scrambler and Descrambler Parameters
Parameter Range Description
Enable TX scrambler (10GBASE-R/Interlaken) On / Off Enables the scrambler function. This option is available for the Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the scrambler in Basic (Enhanced PCS) mode when the block synchronizer is enabled and with 66:32, 66:40, or 66:64 gear box ratios.
TX scrambler seed (10GBASE-R/Interlaken) User‑specified 58-bit value You must provide a non-zero seed for the Interlaken protocol. For a multi-lane Interlaken Transceiver Native PHY IP, the first lane scrambler has this seed. For other lanes' scrambler, this seed is increased by 1 per each lane. The initial seed for 10GBASE-R is 0x03FFFFFFFFFFFFFF. This parameter is required for the 10GBASE‑R and Interlaken protocols.
Enable RX descrambler (10GBASE-R/Interlaken) On / Off Enables the descrambler function. This option is available for Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the descrambler in Basic (Enhanced PCS) mode with the block synchronizer enabled and with 66:32, 66:40, or 66:64 gear box ratios.
Table 33.  Interlaken Disparity Generator and Checker Parameters
Parameter Range Description
Enable Interlaken TX disparity generator On / Off When you turn on this option, the Enhanced PCS enables the disparity generator. This option is available for the Interlaken protocol.
Enable Interlaken RX disparity checker On / Off When you turn on this option, the Enhanced PCS enables the disparity checker. This option is available for the Interlaken protocol.
Enable Interlaken TX random disparity bit On / Off Enables the Interlaken random disparity bit. When enabled, a random number is used as disparity bit which saves one cycle of latency.
Table 34.   Block Synchronizer Parameters
Parameter Range Description
Enable RX block synchronizer On / Off When you turn on this option, the Enhanced PCS enables the RX block synchronizer. This options is available for the Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols.
Enable rx_enh_blk_lock port On / Off Enables the rx_enh_blk_lock port. When you enable the block synchronizer, this signal is asserted to indicate that the block delineation has been achieved.
Table 35.  Gearbox Parameters
Parameter Range Description
Enable TX data bitslip On / Off When you turn on this option, the TX gearbox operates in bitslip mode. The tx_enh_bitslip port controls number of bits which TX parallel data slips before going to the PMA.
Enable TX data polarity inversion On / Off When you turn on this option, the polarity of TX data is inverted. This allows you to correct incorrect placement and routing on the PCB.
Enable RX data bitslip On / Off When you turn on this option, the Enhanced PCS RX block synchronizer operates in bitslip mode. When enabled, the rx_bitslip port is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the PCS.
Enable RX data polarity inversion On / Off When you turn on this option, the polarity of the RX data is inverted. This allows you to correct incorrect placement and routing on the PCB.
Enable tx_enh_bitslip port On / Off Enables the tx_enh_bitslip port. When TX bit slip is enabled, this signal controls the number of bits which TX parallel data slips before going to the PMA.
Enable rx_bitslip port On / Off Enables the rx_bitslip port. When RX bit slip is enabled, the rx_bitslip signal is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the PCS. This port is shared between Standard PCS and Enhanced PCS.
Table 36.  KR-FEC Parameters
Parameter Range Description
Enable RX KR-FEC error marking On/Off When you turn on this option, the decoder asserts both sync bits (2'b11) when it detects an uncorrectable error. This feature increases the latency through the KR-FEC decoder.
Error marking type 10G, 40G Specifies the error marking type (10G or 40G).
Enable KR-FEC TX error insertion On/Off Enables the error insertion feature of the KR-FEC encoder. This feature allows you to insert errors by corrupting data starting a bit 0 of the current word.
KR-FEC TX error insertion spacing User Input (1 bit to 15 bit) Specifies the spacing of the KR-FEC TX error insertion.
Enable tx_enh_frame port On/Off

Enables the tx_enh_frame port. Asynchronous status flag output of the TX KR-FEC that signifies the beginning of the generated KR-FEC frame.

Enable rx_enh_frame port On/Off Enables the rx_enh_frame port. Asynchronous status flag output of the RX KR-FEC that signifies the beginning of the received KR-FEC frame.
Enable rx_enh_frame_diag_status port On/Off Enables the rx_enh_frame_diag_status port. Asynchronous status flag output of the RX KR-FEC that indicates the status of the current received KR-FEC frame.
  • 00: No error
  • 01: Correctable error
  • 10: Uncorrectable error
  • 11: Reset condition/pre-lock condition

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