L- and H-Tile Transceiver PHY User Guide

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ID 683621
Date 12/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile 3. PLLs and Clock Networks 4. Resetting Transceiver Channels 5. Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture 6. Reconfiguration Interface and Dynamic Reconfiguration 7. Calibration 8. Debugging Transceiver Links A. Logical View of the L-Tile/H-Tile Transceiver Registers
1. Overview x
1.1. L-Tile/H-Tile Layout in Stratix® 10 Device Variants 1.2. L-Tile/H-Tile Counts in Stratix® 10 Devices and Package Variants 1.3. L-Tile/H-Tile Building Blocks 1.4. Overview Revision History
1.1. L-Tile/H-Tile Layout in Stratix® 10 Device Variants x
1.1.1. Stratix® 10 GX/SX H-Tile Configurations 1.1.2. Stratix® 10 TX H-Tile and E-Tile Configurations 1.1.3. Stratix® 10 MX H-Tile and E-Tile Configurations
1.3. L-Tile/H-Tile Building Blocks x
1.3.1. Transceiver Bank Architecture 1.3.2. Transceiver Channel Types 1.3.3. GX and GXT Channel Placement Guidelines 1.3.4. GXT Channel Usage 1.3.5. PLL and Clock Networks 1.3.6. Ethernet Hard IP 1.3.7. PCIe Gen1/Gen2/Gen3 Hard IP Block
1.3.2. Transceiver Channel Types x
1.3.2.1. GX Channel 1.3.2.2. GXT Channel
1.3.5. PLL and Clock Networks x
1.3.5.1. PLLs 1.3.5.2. Input Reference Clock Sources 1.3.5.3. Transceiver Clock Network
1.3.5.1. PLLs x
1.3.5.1.1. Transceiver Phase-Locked Loops 1.3.5.1.2. Clock Generation Block (CGB)
1.3.5.3. Transceiver Clock Network x
1.3.5.3.1. x1 Clock Lines 1.3.5.3.2. x6 Clock Lines 1.3.5.3.3. x24 Clock Lines 1.3.5.3.4. GXT Clock Network
1.3.6. Ethernet Hard IP x
1.3.6.1. 100G Ethernet MAC Hard IP 1.3.6.2. 100G Configuration
2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile x
2.1. Transceiver Design IP Blocks 2.2. Transceiver Design Flow 2.3. Configuring the Native PHY IP Core 2.4. Using the Stratix® 10 L-Tile/H-Tile Transceiver Native PHY Stratix® 10 FPGA IP Core 2.5. Implementing the PHY Layer for Transceiver Protocols 2.6. Unused or Idle Transceiver Channels 2.7. Simulating the Native PHY IP Core 2.8. Implementing the Transceiver Native PHY Layer in L-Tile/H-Tile Revision History
2.2. Transceiver Design Flow x
2.2.1. Select the PLL IP Core 2.2.2. Reset Controller 2.2.3. Create Reconfiguration Logic 2.2.4. Connect the Native PHY IP Core to the PLL IP Core and Reset Controller 2.2.5. Connect Datapath 2.2.6. Modify Native PHY IP Core SDC 2.2.7. Compile the Design 2.2.8. Verify Design Functionality
2.3. Configuring the Native PHY IP Core x
2.3.1. Protocol Presets 2.3.2. GXT Channels 2.3.3. General and Datapath Parameters 2.3.4. PMA Parameters 2.3.5. PCS-Core Interface Parameters 2.3.6. Analog PMA Settings Parameters 2.3.7. Enhanced PCS Parameters 2.3.8. Standard PCS Parameters 2.3.9. PCS Direct Datapath Parameters 2.3.10. Dynamic Reconfiguration Parameters 2.3.11. Generation Options Parameters 2.3.12. PMA, Calibration, and Reset Ports 2.3.13. PCS-Core Interface Ports 2.3.14. Enhanced PCS Ports 2.3.15. Standard PCS Ports 2.3.16. Transceiver PHY PCS-to-Core Interface Reference Port Mapping 2.3.17. IP Core File Locations
2.3.14. Enhanced PCS Ports x
2.3.14.1. Enhanced PCS TX and RX Control Ports
2.3.16. Transceiver PHY PCS-to-Core Interface Reference Port Mapping x
2.3.16.1. PCS-Core Interface Ports: Enhanced PCS 2.3.16.2. PCS-Core Interface Ports: Standard PCS 2.3.16.3. PCS-Core Interface Ports: PCS-Direct
2.4. Using the Stratix® 10 L-Tile/H-Tile Transceiver Native PHY Stratix® 10 FPGA IP Core x
2.4.1. PMA Functions 2.4.2. PCS Functions 2.4.3. Deterministic Latency Use Model 2.4.4. Debug Functions
2.4.1. PMA Functions x
2.4.1.1. TX PMA Use Model 2.4.1.2. RX PMA Use Model
2.4.1.2. RX PMA Use Model x
2.4.1.2.1. Using RX in Manual Mode 2.4.1.2.2. Using RX in Adaptive Mode 2.4.1.2.3. Setting RX PMA Adaptation Modes 2.4.1.2.4. Register Sequences
2.4.2. PCS Functions x
2.4.2.1. Receiver Word Alignment 2.4.2.2. Receiver Clock Compensation 2.4.2.3. Encoding/Decoding 2.4.2.4. Running Disparity Control and Check 2.4.2.5. FIFO Operation for the Enhanced PCS 2.4.2.6. Polarity Inversion 2.4.2.7. Data Bitslip 2.4.2.8. Bit Reversal 2.4.2.9. Byte Reversal 2.4.2.10. Double Rate Transfer Mode 2.4.2.11. Asynchronous Data Transfer 2.4.2.12. Low Latency
2.4.2.1. Receiver Word Alignment x
2.4.2.1.1. Word Alignment Using the Standard PCS 2.4.2.1.2. Word Alignment Using the Enhanced PCS
2.4.2.2. Receiver Clock Compensation x
2.4.2.2.1. Clock Compensation Using the Standard PCS 2.4.2.2.2. Clock Compensation Using the Enhanced PCS
2.4.2.3. Encoding/Decoding x
2.4.2.3.1. 8B/10B Encoder and Decoder 2.4.2.3.2. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 2.4.2.3.3. KR-FEC Functionality for 64B/66B Based Protocols
2.4.2.4. Running Disparity Control and Check x
2.4.2.4.1. 8B/10B TX Disparity Control
2.4.2.5. FIFO Operation for the Enhanced PCS x
2.4.2.5.1. Enhanced PCS FIFO Operation
2.4.2.6. Polarity Inversion x
2.4.2.6.1. TX Data Polarity Inversion 2.4.2.6.2. RX Data Polarity Inversion
2.4.2.7. Data Bitslip x
2.4.2.7.1. TX Data Bitslip 2.4.2.7.2. RX Data Bitslip
2.4.2.8. Bit Reversal x
2.4.2.8.1. Transmitter Bit Reversal 2.4.2.8.2. Receiver Bit Reversal
2.4.2.9. Byte Reversal x
2.4.2.9.1. Transmitter Byte Reversal 2.4.2.9.2. Receiver Byte Reversal
2.4.2.10. Double Rate Transfer Mode x
2.4.2.10.1. Word Marking Bits 2.4.2.10.2. How to Implement Double Rate Transfer Mode
2.4.2.11. Asynchronous Data Transfer x
2.4.2.11.1. FPGA Fabric to Transceiver Transfer 2.4.2.11.2. Transceiver to FPGA Fabric Transfer
2.4.2.12. Low Latency x
2.4.2.12.1. How to Enable Low Latency in Basic (Standard PCS) 2.4.2.12.2. How to Enable Low Latency in Basic (Enhanced PCS)
2.4.3. Deterministic Latency Use Model x
2.4.3.1. Phase-measuring FIFOs
2.4.3.1. Phase-measuring FIFOs x
2.4.3.1.1. Primary Use Model 2.4.3.1.2. FIFO Latency Calculation
2.4.4. Debug Functions x
2.4.4.1. Pattern Generators and Verifiers 2.4.4.2. PRBS Soft Accumulators 2.4.4.3. Loopback 2.4.4.4. On-die Instrumentation
2.4.4.1. Pattern Generators and Verifiers x
2.4.4.1.1. Pattern Generator and Verifier Use Model 2.4.4.1.2. Square Wave Pattern Generator 2.4.4.1.3. PRBS Generator and Verifier 2.4.4.1.4. PRBS Control and Status Ports 2.4.4.1.5. Enabling and Disabling the PRBS Generator and PRBS Verifier
2.4.4.2. PRBS Soft Accumulators x
2.4.4.2.1. PRBS Soft Accumulators Use Model
2.4.4.3. Loopback x
2.4.4.3.1. Enabling and Disabling Loopback
2.4.4.4. On-die Instrumentation x
2.4.4.4.1. On-die Instrumentation Overview 2.4.4.4.2. Preserving ODI Performance 2.4.4.4.3. How to Enable ODI 2.4.4.4.4. Scanning the Horizontal Eye Opening 2.4.4.4.5. Scanning the Horizontal and Vertical Phases 2.4.4.4.6. How to Disable ODI 2.4.4.4.7. Horizontal Phase Step Mapping
2.5. Implementing the PHY Layer for Transceiver Protocols x
2.5.1. PCI Express (PIPE) 2.5.2. Interlaken 2.5.3. Ethernet 2.5.4. CPRI
2.5.1. PCI Express (PIPE) x
2.5.1.1. Transceiver Channel Datapath for PIPE 2.5.1.2. Supported PIPE Features 2.5.1.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes 2.5.1.4. How to Implement PCI Express (PIPE) in Stratix® 10 Transceivers 2.5.1.5. Native PHY IP Core Parameter Settings for PIPE 2.5.1.6. fPLL IP Core Parameter Settings for PIPE 2.5.1.7. ATX PLL IP Core Parameter Settings for PIPE 2.5.1.8. Native PHY IP Core Ports for PIPE 2.5.1.9. fPLL Ports for PIPE 2.5.1.10. ATX PLL Ports for PIPE 2.5.1.11. Preset Mappings to TX De-emphasis 2.5.1.12. How to Place Channels for PIPE Configurations 2.5.1.13. Link Equalization for Gen3 2.5.1.14. Timing Closure Recommendations
2.5.1.2. Supported PIPE Features x
2.5.1.2.1. Gen1/Gen2 Features 2.5.1.2.2. Gen3 Features
2.5.1.12. How to Place Channels for PIPE Configurations x
2.5.1.12.1. Master Channel in Bonded Configurations
2.5.2. Interlaken x
2.5.2.1. Interlaken Configuration Clocking and Bonding
2.5.2.1. Interlaken Configuration Clocking and Bonding x
2.5.2.1.1. x24 Clock Bonding Scenario 2.5.2.1.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine
2.5.3. Ethernet x
2.5.3.1. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with KR FEC Variants 2.5.3.2. 40GBASE-R with KR FEC Variant
2.5.3.1. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with KR FEC Variants x
2.5.3.1.1. The XGMII Interface Scheme in 10GBASE-R
2.5.4. CPRI x
2.5.4.1. CPRI Line Rate Revisions 2.5.4.2. Transceiver Channel Datapath and Clocking for CPRI 2.5.4.3. Supported Features for CPRI 2.5.4.4. Deterministic Latency
2.5.4.2. Transceiver Channel Datapath and Clocking for CPRI x
2.5.4.2.1. TX PLL Selection for CPRI 2.5.4.2.2. Auto-Negotiation
2.5.4.3. Supported Features for CPRI x
2.5.4.3.1. Word Aligner in Manual Mode for CPRI
2.7. Simulating the Native PHY IP Core x
2.7.1. How to Specify Third-Party RTL Simulators 2.7.2. Scripting IP Simulation 2.7.3. Custom Simulation Flow
2.7.2. Scripting IP Simulation x
2.7.2.1. Generating a Combined Simulator Setup Script 2.7.2.2. Steps for a .do file for Simulation
2.7.3. Custom Simulation Flow x
2.7.3.1. How to Use the Simulation Library Compiler 2.7.3.2. Custom Simulation Scripts
3. PLLs and Clock Networks x
3.1. PLLs 3.2. Input Reference Clock Sources 3.3. Transmitter Clock Network 3.4. Clock Generation Block 3.5. FPGA Fabric-Transceiver Interface Clocking 3.6. Double Rate Transfer Mode 3.7. Transmitter Data Path Interface Clocking 3.8. Receiver Data Path Interface Clocking 3.9. Channel Bonding 3.10. PLL Cascading Clock Network 3.11. Using PLLs and Clock Networks 3.12. PLLs and Clock Networks Revision History
3.1. PLLs x
3.1.1. ATX PLL 3.1.2. fPLL 3.1.3. CMU PLL
3.1.1. ATX PLL x
3.1.1.1. ATX PLL to fPLL Spacing Requirements 3.1.1.2. Using the ATX PLL for GXT Channels 3.1.1.3. GXT Implementation Usage Restrictions for ATX PLL GX & MCGB 3.1.1.4. Instantiating the ATX PLL IP Core 3.1.1.5. ATX PLL IP Core - Parameters, Settings, and Ports
3.1.2. fPLL x
3.1.2.1. Instantiating the fPLL IP Core 3.1.2.2. fPLL IP Core Constraints 3.1.2.3. fPLL IP Core - Parameters, Settings, and Ports
3.1.3. CMU PLL x
3.1.3.1. Instantiating CMU PLL IP Core 3.1.3.2. CMU PLL IP Core - Parameters, Settings, and Ports
3.2. Input Reference Clock Sources x
3.2.1. Dedicated Reference Clock Pins 3.2.2. Receiver Input Pins 3.2.3. PLL Cascading as an Input Reference Clock Source 3.2.4. Reference Clock Network 3.2.5. Core Clock as an Input Reference Clock
3.2.1. Dedicated Reference Clock Pins x
3.2.1.1. Reference Clock I/O Standard 3.2.1.2. Dedicated Reference Clock Pin Termination (XCVR_S10_REFCLK_TERM_TRISTATE)
3.3. Transmitter Clock Network x
3.3.1. x1 Clock Lines 3.3.2. x6 Clock Lines 3.3.3. x24 Clock Lines 3.3.4. GXT Clock Network 3.3.5. HCLK Network
3.9. Channel Bonding x
3.9.1. PMA Bonding 3.9.2. PMA and PCS Bonding 3.9.3. Selecting Channel Bonding Schemes 3.9.4. Skew Calculations
3.9.1. PMA Bonding x
3.9.1.1. x6/x24 Bonding
3.11. Using PLLs and Clock Networks x
3.11.1. Non-bonded Configurations 3.11.2. Bonded Configurations 3.11.3. Implementing PLL Cascading 3.11.4. Mix and Match Example
3.11.1. Non-bonded Configurations x
3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration 3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration 3.11.1.3. Implementing Multi-Channel x24 Non-Bonded Configuration
3.11.2. Bonded Configurations x
3.11.2.1. Implementing x6/x24 Bonding Mode
4. Resetting Transceiver Channels x
4.1. When Is Reset Required? 4.2. Transceiver PHY Reset Controller Stratix® 10 FPGA IP Implementation 4.3. How Do I Reset? 4.4. Using PCS Reset Status Port 4.5. Using Transceiver PHY Reset Controller Stratix® 10 FPGA IP 4.6. Using a User-Coded Reset Controller 4.7. Combining Status or PLL Lock Signals with User Coded Reset Controller 4.8. Resetting Transceiver Channels Revision History
4.3. How Do I Reset? x
4.3.1. Recommended Reset Sequence 4.3.2. Transceiver Blocks Affected by Reset and Power-down Signals
4.3.1. Recommended Reset Sequence x
4.3.1.1. Resetting the Transmitter After Power Up 4.3.1.2. Resetting the Transmitter During Device Operation 4.3.1.3. Resetting the Receiver After Power Up 4.3.1.4. Resetting the Receiver During Device Operation (Auto Mode) 4.3.1.5. Clock Data Recovery in Manual Lock Mode 4.3.1.6. Special TX PCS Reset Release Sequence
4.3.1.5. Clock Data Recovery in Manual Lock Mode x
4.3.1.5.1. Control Settings for CDR Manual Lock Mode 4.3.1.5.2. Resetting the Transceiver in CDR Manual Lock Mode
4.3.1.6. Special TX PCS Reset Release Sequence x
4.3.1.6.1. TX Core FIFO in Interlaken/Basic Mode 4.3.1.6.2. Double Rate Transfer Mode enabled 4.3.1.6.3. TX Gearbox Ratio *:67
4.5. Using Transceiver PHY Reset Controller Stratix® 10 FPGA IP x
4.5.1. Parameterizing Transceiver PHY Reset Controller Stratix® 10 FPGA IP 4.5.2. Transceiver PHY Reset Controller Stratix® 10 FPGA IP Parameters 4.5.3. Transceiver PHY Reset Controller Stratix® 10 FPGA IP Interfaces 4.5.4. Transceiver PHY Reset Controller Stratix® 10 FPGA IP Resource Utilization
4.6. Using a User-Coded Reset Controller x
4.6.1. User-Coded Reset Controller Signals
5. Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture x
5.1. PMA Architecture 5.2. Enhanced PCS Architecture 5.3. Stratix® 10 Standard PCS Architecture 5.4. Stratix® 10 PCI Express Gen3 PCS Architecture 5.5. PCS Support for GXT Channels 5.6. Square Wave Generator 5.7. PRBS Pattern Generator 5.8. PRBS Pattern Verifier 5.9. Loopback Modes 5.10. Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture Revision History
5.1. PMA Architecture x
5.1.1. Transmitter PMA 5.1.2. Receiver PMA
5.1.1. Transmitter PMA x
5.1.1.1. Serializer 5.1.1.2. Transmitter Buffer
5.1.1.2. Transmitter Buffer x
5.1.1.2.1. High-Speed Differential I/O 5.1.1.2.2. Programmable Output Differential Voltage 5.1.1.2.3. Programmable Pre-Emphasis
5.1.2. Receiver PMA x
5.1.2.1. Receiver Buffer 5.1.2.2. Clock Data Recovery (CDR) Unit 5.1.2.3. Deserializer
5.1.2.1. Receiver Buffer x
5.1.2.1.1. Programmable Differential On-Chip Termination (OCT) 5.1.2.1.2. Signal Detector 5.1.2.1.3. Continuous Time Linear Equalization (CTLE) 5.1.2.1.4. Variable Gain Amplifier (VGA) 5.1.2.1.5. Adaptive Parametric Tuning (ADAPT) Engine 5.1.2.1.6. Decision Feedback Equalization (DFE) 5.1.2.1.7. On-Die Instrumentation
5.1.2.2. Clock Data Recovery (CDR) Unit x
5.1.2.2.1. Lock-to-Reference Mode 5.1.2.2.2. Lock-to-Data Mode 5.1.2.2.3. CDR Lock Modes
5.2. Enhanced PCS Architecture x
5.2.1. Transmitter Datapath 5.2.2. Receiver Datapath 5.2.3. RX KR FEC Blocks
5.2.1. Transmitter Datapath x
5.2.1.1. TX Core FIFO 5.2.1.2. TX PCS FIFO 5.2.1.3. Interlaken Frame Generator 5.2.1.4. Interlaken CRC-32 Generator 5.2.1.5. 64B/66B Encoder and Transmitter State Machine (TX SM) 5.2.1.6. Scrambler 5.2.1.7. Interlaken Disparity Generator 5.2.1.8. TX Gearbox, TX Bitslip and Polarity Inversion 5.2.1.9. KR FEC Blocks
5.2.2. Receiver Datapath x
5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion 5.2.2.2. Block Synchronizer 5.2.2.3. Interlaken Disparity Checker 5.2.2.4. Descrambler 5.2.2.5. Interlaken Frame Synchronizer 5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) 5.2.2.7. 10GBASE-R Bit-Error Rate (BER) Checker 5.2.2.8. Interlaken CRC-32 Checker 5.2.2.9. RX PCS FIFO 5.2.2.10. RX Core FIFO
5.2.2.9. RX PCS FIFO x
5.2.2.9.1. Phase Compensation Mode 5.2.2.9.2. Register Mode
5.2.2.10. RX Core FIFO x
5.2.2.10.1. Phase Compensation Mode 5.2.2.10.2. Register Mode 5.2.2.10.3. Basic Mode 5.2.2.10.4. Interlaken Mode 5.2.2.10.5. 10GBASE-R Mode
5.3. Stratix® 10 Standard PCS Architecture x
5.3.1. Transmitter Datapath 5.3.2. Receiver Datapath
5.3.1. Transmitter Datapath x
5.3.1.1. TX Core FIFO 5.3.1.2. TX PCS FIFO 5.3.1.3. Byte Serializer 5.3.1.4. 8B/10B Encoder 5.3.1.5. Polarity Inversion Feature 5.3.1.6. TX Bit Slip
5.3.1.3. Byte Serializer x
5.3.1.3.1. Bonded Byte Serializer 5.3.1.3.2. Byte Serializer Disabled Mode 5.3.1.3.3. Byte Serializer Serialize x2 Mode 5.3.1.3.4. Byte Serializer Serialize x4 Mode
5.3.1.4. 8B/10B Encoder x
5.3.1.4.1. 8B/10B Encoder Control Code Encoding 5.3.1.4.2. 8B/10B Encoder Reset Condition 5.3.1.4.3. 8B/10B Encoder Idle Character Replacement Feature 5.3.1.4.4. 8B/10B Encoder Current Running Disparity Control Feature 5.3.1.4.5. 8B/10B Encoder Bit Reversal Feature 5.3.1.4.6. 8B/10B Encoder Byte Reversal Feature
5.3.2. Receiver Datapath x
5.3.2.1. Word Aligner 5.3.2.2. RX Polarity Inversion Feature 5.3.2.3. Rate Match FIFO 5.3.2.4. 8B/10B Decoder 5.3.2.5. PRBS Verifier 5.3.2.6. Byte Deserializer 5.3.2.7. RX PCS FIFO 5.3.2.8. RX Core FIFO
5.3.2.1. Word Aligner x
5.3.2.1.1. Word Aligner Bitslip Mode 5.3.2.1.2. Word Aligner Manual Mode 5.3.2.1.3. Word Aligner Synchronous State Machine Mode 5.3.2.1.4. Word Aligner Deterministic Latency Mode 5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes 5.3.2.1.6. Word Aligner RX Bit Reversal Feature 5.3.2.1.7. Word Aligner RX Byte Reversal Feature
5.3.2.4. 8B/10B Decoder x
5.3.2.4.1. 8B/10B Decoder Control Code Encoding 5.3.2.4.2. 8B/10B Decoder Running Disparity Checker Feature
5.3.2.6. Byte Deserializer x
5.3.2.6.1. Byte Deserializer Disabled Mode 5.3.2.6.2. Byte Deserializer Deserialize x2 Mode 5.3.2.6.3. Byte Deserializer Deserialize x4 Mode 5.3.2.6.4. Bonded Byte Deserializer 5.3.2.6.5. Byte Ordering Register-Transfer Level (RTL) 5.3.2.6.6. Byte Serializer Effects on Data Propagation at the RX Side 5.3.2.6.7. ModelSim Byte Ordering Analysis
5.4. Stratix® 10 PCI Express Gen3 PCS Architecture x
5.4.1. Transmitter Datapath 5.4.2. Receiver Datapath 5.4.3. PIPE Interface
5.4.1. Transmitter Datapath x
5.4.1.1. TX Core FIFO 5.4.1.2. TX PCS FIFO 5.4.1.3. Gearbox
5.4.2. Receiver Datapath x
5.4.2.1. Block Synchronizer 5.4.2.2. Rate Match FIFO 5.4.2.3. RX PCS FIFO 5.4.2.4. RX Core FIFO
5.4.3. PIPE Interface x
5.4.3.1. Auto-Speed Negotiation 5.4.3.2. Clock Data Recovery Control
6. Reconfiguration Interface and Dynamic Reconfiguration x
6.1. Reconfiguring Channel and PLL Blocks 6.2. Interacting with the Reconfiguration Interface 6.3. Multiple Reconfiguration Profiles 6.4. Arbitration 6.5. Recommendations for Dynamic Reconfiguration 6.6. Steps to Perform Dynamic Reconfiguration 6.7. Direct Reconfiguration Flow 6.8. Native PHY IP or PLL IP Core Guided Reconfiguration Flow 6.9. Reconfiguration Flow for Special Cases 6.10. Changing Analog PMA Settings 6.11. Ports and Parameters 6.12. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks 6.13. Embedded Debug Features 6.14. Timing Closure Recommendations 6.15. Unsupported Features 6.16. Transceiver Register Map 6.17. Reconfiguration Interface and Dynamic Revision History
6.2. Interacting with the Reconfiguration Interface x
6.2.1. Reading from the Reconfiguration Interface 6.2.2. Writing to the Reconfiguration Interface
6.3. Multiple Reconfiguration Profiles x
6.3.1. Configuration Files 6.3.2. Embedded Reconfiguration Streamer
6.6. Steps to Perform Dynamic Reconfiguration x
6.6.1. Channel Reconfiguration 6.6.2. PLL Reconfiguration
6.9. Reconfiguration Flow for Special Cases x
6.9.1. Switching Transmitter PLL 6.9.2. Switching Reference Clocks 6.9.3. Reconfiguring Between GX and GXT Channels
6.9.2. Switching Reference Clocks x
6.9.2.1. ATX Reference Clock Switching 6.9.2.2. fPLL Reference Clock Switching 6.9.2.3. CDR and CMU Reference Clock Switching
6.13. Embedded Debug Features x
6.13.1. Native PHY Debug Master Endpoint (NPDME) 6.13.2. Optional Reconfiguration Logic
6.13.2. Optional Reconfiguration Logic x
6.13.2.1. Capability Registers 6.13.2.2. Control and Status Registers 6.13.2.3. PRBS Soft Accumulators
7. Calibration x
7.1. Reconfiguration Interface and Arbitration with PreSICE (Precision Signal Integrity Calibration Engine) 7.2. Calibration Registers 7.3. Power-up Calibration 7.4. Background Calibration 7.5. User Recalibration 7.6. Calibration Revision History
7.2. Calibration Registers x
7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers 7.2.2. User Recalibration Enable Registers 7.2.3. Capability Registers Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals 7.2.4. Rate Switch Flag Register
7.2.2. User Recalibration Enable Registers x
7.2.2.1. Transceiver Channel Calibration Registers 7.2.2.2. ATX PLL/fPLL/CMU PLL Calibration Registers
7.5. User Recalibration x
7.5.1. Recalibrating a Duplex Channel (Both PMA TX and PMA RX) 7.5.2. Recalibrating the PMA RX Only in a Duplex Channel 7.5.3. Recalibrating the PMA TX Only in a Duplex Channel 7.5.4. Recalibrating a PMA Simplex RX Without a Simplex TX Merged into the Same Physical Channel 7.5.5. Recalibrating a PMA Simplex TX Without a Simplex RX Merged into the Same Physical Channel 7.5.6. Recalibrating Only a PMA Simplex RX in a Simplex TX Merged Physical Channel 7.5.7. Recalibrating Only a PMA Simplex TX in a Simplex RX Merged Physical Channel 7.5.8. Recalibrating the fPLL 7.5.9. Recalibrating the ATX PLL 7.5.10. Recalibrating the CMU PLL When it is Used as a TX PLL
8. Debugging Transceiver Links x
8.1. Transceiver Toolkit GUI 8.2. Transceiver Debugging Flow Walkthrough 8.3. Linking Hardware Resource for Multiple FPGAs 8.4. Troubleshooting Common Errors 8.5. Debugging Transceiver Links Revision History
8.1. Transceiver Toolkit GUI x
8.1.1. Collection View
8.2. Transceiver Debugging Flow Walkthrough x
8.2.1. Enabling Transceiver Toolkit Support 8.2.2. Programming the Design into an Intel FPGA 8.2.3. Loading the Design to the Transceiver Toolkit 8.2.4. Creating Transceiver Links 8.2.5. Verifying Hardware Connections 8.2.6. Running Link Tests
8.2.4. Creating Transceiver Links x
8.2.4.1. Transceiver Toolkit Parameter Settings
8.2.6. Running Link Tests x
8.2.6.1. Running BER Tests 8.2.6.2. Link Optimization Tests 8.2.6.3. Running Eye Viewer Tests
8.3. Linking Hardware Resource for Multiple FPGAs x
8.3.1. Linking One Design to One Device 8.3.2. Linking Two Designs to Two Devices 8.3.3. Linking One Design on Two Devices 8.3.4. Linking Designs and Devices on Separate Boards
A. Logical View of the L-Tile/H-Tile Transceiver Registers x
A.1. ATX_PLL Logical Register Map A.2. CMU_PLL Logical Register Map A.3. FPLL Logical Register Map A.4. Channel Logical Register Map A.5. Transmitter PLL Switching Register Map A.6. Logical View Register Map of the L-Tile/H-Tile Transceiver Registers Revision History
A.1. ATX_PLL Logical Register Map x
A.1.1. ATX PLL Calibration A.1.2. Optional Reconfiguration Logic ATX PLL- Capability A.1.3. Optional Reconfiguration Logic ATX PLL- Control & Status A.1.4. Embedded Streamer (ATX PLL) A.1.5. Updating ATX PLL Fractional Multiply Factor (K) Value
A.2. CMU_PLL Logical Register Map x
A.2.1. CDR/CMU and PMA Calibration A.2.2. Optional Reconfiguration Logic CMU PLL- Capability A.2.3. Optional Reconfiguration Logic CMU PLL- Control & Status A.2.4. Embedded Streamer (CMU PLL)
A.3. FPLL Logical Register Map x
A.3.1. fPLL Calibration A.3.2. Optional Reconfiguration Logic fPLL-Capability A.3.3. Optional Reconfiguration Logic fPLL-Control & Status A.3.4. Embedded Streamer (fPLL) A.3.5. Updating fPLL Fractional Multiply Factor (K) Value
A.4. Channel Logical Register Map x
A.4.1. Transmitter PMA Logical Register Map A.4.2. Receiver PMA Logical Register Map A.4.3. Pattern Generators and Checkers A.4.4. Loopback A.4.5. Optional Reconfiguration Logic PHY- Capability A.4.6. Optional Reconfiguration Logic PHY- Control & Status A.4.7. Embedded Streamer (Native PHY) A.4.8. Static Polarity Inversion A.4.9. Reset A.4.10. CDR/CMU and PMA Calibration
A.4.1. Transmitter PMA Logical Register Map x
A.4.1.1. Pre-emphasis A.4.1.2. VOD A.4.1.3. TX Compensation A.4.1.4. Slew Rate A.4.1.5. TX Termination
A.4.2. Receiver PMA Logical Register Map x
A.4.2.1. RX Bandwidth Selection A.4.2.2. RX Termination A.4.2.3. Setting RX PMA Adaptation Modes A.4.2.4. Manual CTLE A.4.2.5. Manual VGA A.4.2.6. Adaptation Control - Start A.4.2.7. Adaptation Control - Stop A.4.2.8. Adapted Value Readout
A.4.3. Pattern Generators and Checkers x
A.4.3.1. Square Wave Generator A.4.3.2. PRBS Generator A.4.3.3. PRBS Verifier A.4.3.4. Other registers needed for PRBS Verifier A.4.3.5. PRBS Soft Accumulators
1. Overview
2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile
3. PLLs and Clock Networks
4. Resetting Transceiver Channels
5. Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture
6. Reconfiguration Interface and Dynamic Reconfiguration
7. Calibration
8. Debugging Transceiver Links
A. Logical View of the L-Tile/H-Tile Transceiver Registers

7.2.3. Capability Registers

Capability registers allow you to read calibration status through Avalon® memory-mapped interface reconfiguration. They are soft logic and reside in the FPGA fabric.

Reading capability registers does not require bus arbitration. You can read them during the calibration process.

To use capability registers to check calibration status, you must enable the capability registers when generating the Native PHY or PLL IP cores. To enable the capability registers, select the Enable capability registers option in the Dynamic Reconfiguration tab.

The tx_cal_busy and rx_cal_busy signals from the hard PHY are from the same hardware and change the state (high/low) concurrently during calibration. The register bits 0x481[5:4] are defined to solve this issue. This prevents a TX channel being affected by RX calibration, or an RX channel being affected by TX calibration. If you want rx_cal_busy unchanged during the TX calibration, you must set 0x481[5] to 0x0 before returning the bus to PreSICE. The channel RX is not reset due to the TX calibration. If you wanttx_cal_busy unchanged during the RX calibration, you must set 0x481[4] to 0x0 before returning the bus to PreSICE. The channel TX is not reset due to the RX calibration. If you accidentally write 0x00 to 0x481[5:4], the tx_cal_busy or rx_cal_busy output ports are never activated to high. Neither of the 0x481[1:0] registers assert either. This feature cannot be enabled when channel merging is involved or when a TX simplex and a RX simplex are merged into a single physical channel.

Note: When you merge a TX Simplex and a RX Simplex into the same physical channel, you cannot enable the background calibration feature.

Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals

Figure 251. An Example of an AND Gate used as Customized LogicThe customized gates shown in the following figure are an example and not a unique solution
The capability register is not available for merging a Simplex TX and a Simplex RX signal into the same physical channel. The tx_cal_busy_out and rx_cal_busy_out signals share the same port. So, you should build customized gating logic to separate them.
  • The tx_cal_busy_out_en signal enables the tx_cal_busy output.
  • The rx_cal_busy_out_en signal enables the rx_cal_busy output.
  • At power up, tx_cal_busy_out_en and rx_cal_busy_out_en should be set to “1”.
  • At normal operation:
    • When the RX is calibrating, setting tx_cal_busy_out_en to “0” and rx_cal_busy_out_en to “1” disables tx_cal_busy, so the TX does not reset while RX is calibrating.
    • When the TX is calibrating, setting rx_cal_busy_out_en to “0” and tx_cal_busy_out_en to “1” disables rx_cal_busy, so the RX does not reset while TX is calibrating.

You can use the PMA 0x481[2] register to check bus arbitration through Avalon® memory-mapped interface reconfiguration. This feature is available whether or not Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled in the Dynamic Reconfiguration tab. The ATX PLL and fPLL use the 0x480[2] register for bus arbitration status.

Table 170.  PMA Capability Registers for Calibration Status
Bit Description
0x481[5]

PMA channel rx_cal_busy output enable.52 The power up default value is 0x1.

0x1: The rx_cal_busy output and 0x481[1] are asserted high whenever PMA TX or RX calibration is running.

0x0: The rx_cal_busy output or 0x481[1] are never asserted high.

0x481[4]

PMA channel tx_cal_busy output enable. The power up default value is 0x1.

0x1: The tx_cal_busy output and 0x481[0] are asserted high whenever PMA TX or RX calibration is running.

0x0: The tx_cal_busy output or 0x481[0] are never asserted high.

0x481[2] PreSICE Avalon® memory-mapped interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x1: PreSICE is controlling the internal configuration bus.

0x0: The user has control of the internal configuration bus.

0x481[1]

PMA channel rx_cal_busy active high

0x1: PMA RX calibration is running

0x0: PMA RX calibration is done
0x481[0]

PMA channel tx_cal_busy active high

0x1: PMA TX calibration is running

0x0: PMA TX calibration is done
Table 171.  ATX PLL Capability Registers for Calibration Status
Bit Description
0x480[2] PreSICE Avalon® memory-mapped interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x1: PreSICE is controlling the internal configuration bus.

0x0: The user has control of the internal configuration bus.

0x480[1]

ATX PLL pll_cal_busy

0x1: ATX PLL calibration is running

0x0: ATX PLL calibration is done
Table 172.  fPLL Capability Registers for Calibration Status
Bit Description
0x480[2] PreSICE Avalon® memory-mapped interface control

0x1: PreSICE is controlling the internal configuration bus. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x0: The user has control of the internal configuration bus.

0x480[1]

fPLL pll_cal_busy

0x1: fPLL calibration is running

0x0: fPLL calibration is done
Table 173.  CMU PLL Capability Registers for Calibration Status
Bit Description
0x480[2] PreSICE Avalon® memory-mapped interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x1: PreSICE is controlling the internal configuration bus.

0x0: The user has control of the internal configuration bus.

0x480[1]

CMU PLL pll_cal_busy

0x1: CMU PLL calibration is running

0x0: CMU PLL calibration is done
52 CDR and CMU PLL calibration are part of RX PMA calibration.
Level Two Title