L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Public
Document Table of Contents

7.2.3. Capability Registers

Capability registers allow you to read calibration status through Avalon® memory-mapped interface reconfiguration. They are soft logic and reside in the FPGA fabric.

Reading capability registers does not require bus arbitration. You can read them during the calibration process.

To use capability registers to check calibration status, you must enable the capability registers when generating the Native PHY or PLL IP cores. To enable the capability registers, select the Enable capability registers option in the Dynamic Reconfiguration tab.

The tx_cal_busy and rx_cal_busy signals from the hard PHY are from the same hardware and change the state (high/low) concurrently during calibration. The register bits 0x481[5:4] are defined to solve this issue. This prevents a TX channel being affected by RX calibration, or an RX channel being affected by TX calibration. If you want rx_cal_busy unchanged during the TX calibration, you must set 0x481[5] to 0x0 before returning the bus to PreSICE. The channel RX is not reset due to the TX calibration. If you wanttx_cal_busy unchanged during the RX calibration, you must set 0x481[4] to 0x0 before returning the bus to PreSICE. The channel TX is not reset due to the RX calibration. If you accidentally write 0x00 to 0x481[5:4], the tx_cal_busy or rx_cal_busy output ports are never activated to high. Neither of the 0x481[1:0] registers assert either. This feature cannot be enabled when channel merging is involved or when a TX simplex and a RX simplex are merged into a single physical channel.

Note: When you merge a TX Simplex and a RX Simplex into the same physical channel, you cannot enable the background calibration feature.

Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals

Figure 251. An Example of an AND Gate used as Customized LogicThe customized gates shown in the following figure are an example and not a unique solution
The capability register is not available for merging a Simplex TX and a Simplex RX signal into the same physical channel. The tx_cal_busy_out and rx_cal_busy_out signals share the same port. So, you should build customized gating logic to separate them.
  • The tx_cal_busy_out_en signal enables the tx_cal_busy output.
  • The rx_cal_busy_out_en signal enables the rx_cal_busy output.
  • At power up, tx_cal_busy_out_en and rx_cal_busy_out_en should be set to “1”.
  • At normal operation:
    • When the RX is calibrating, setting tx_cal_busy_out_en to “0” and rx_cal_busy_out_en to “1” disables tx_cal_busy, so the TX does not reset while RX is calibrating.
    • When the TX is calibrating, setting rx_cal_busy_out_en to “0” and tx_cal_busy_out_en to “1” disables rx_cal_busy, so the RX does not reset while TX is calibrating.

You can use the PMA 0x481[2] register to check bus arbitration through Avalon® memory-mapped interface reconfiguration. This feature is available whether or not Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled in the Dynamic Reconfiguration tab. The ATX PLL and fPLL use the 0x480[2] register for bus arbitration status.

Table 170.  PMA Capability Registers for Calibration Status
Bit Description
0x481[5]

PMA channel rx_cal_busy output enable.52 The power up default value is 0x1.

0x1: The rx_cal_busy output and 0x481[1] are asserted high whenever PMA TX or RX calibration is running.

0x0: The rx_cal_busy output or 0x481[1] are never asserted high.

0x481[4]

PMA channel tx_cal_busy output enable. The power up default value is 0x1.

0x1: The tx_cal_busy output and 0x481[0] are asserted high whenever PMA TX or RX calibration is running.

0x0: The tx_cal_busy output or 0x481[0] are never asserted high.

0x481[2] PreSICE Avalon® memory-mapped interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x1: PreSICE is controlling the internal configuration bus.

0x0: The user has control of the internal configuration bus.

0x481[1]

PMA channel rx_cal_busy active high

0x1: PMA RX calibration is running

0x0: PMA RX calibration is done

0x481[0]

PMA channel tx_cal_busy active high

0x1: PMA TX calibration is running

0x0: PMA TX calibration is done

Table 171.  ATX PLL Capability Registers for Calibration Status
Bit Description
0x480[2] PreSICE Avalon® memory-mapped interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x1: PreSICE is controlling the internal configuration bus.

0x0: The user has control of the internal configuration bus.

0x480[1]

ATX PLL pll_cal_busy

0x1: ATX PLL calibration is running

0x0: ATX PLL calibration is done

Table 172.  fPLL Capability Registers for Calibration Status
Bit Description
0x480[2] PreSICE Avalon® memory-mapped interface control

0x1: PreSICE is controlling the internal configuration bus. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x0: The user has control of the internal configuration bus.

0x480[1]

fPLL pll_cal_busy

0x1: fPLL calibration is running

0x0: fPLL calibration is done

Table 173.  CMU PLL Capability Registers for Calibration Status
Bit Description
0x480[2] PreSICE Avalon® memory-mapped interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x1: PreSICE is controlling the internal configuration bus.

0x0: The user has control of the internal configuration bus.

0x480[1]

CMU PLL pll_cal_busy

0x1: CMU PLL calibration is running

0x0: CMU PLL calibration is done

52 CDR and CMU PLL calibration are part of RX PMA calibration.