L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.3.2. Optional Reconfiguration Logic fPLL-Capability

Enables fPLL capabilities to be readable.
Name Address Type Attribute Name Encodings
IP Identifier

0x400[7:0]

0x401[7:0]

0x402[7:0]

0x403[7:0]

read-only fpll_address_id Unique identifier for the PLL instance.
Status Register Enabled

0x404[0]

read-only fpll_status_register_enable Indicates if the status registers have been enabled. 1'b1 indicates the feature is enabled.
Control Register Enabled

0x405[0]

read-only fpll_control_register_enable Indicates if the control registers have been enabled. 1'b1 indicates the feature is enabled.
Master CGB enabled

0x410[0]

read-only fpll_mcgb_enable Indicates if the Master CGB is enabled. 1'b1 indicates the master CGB is enabled.

Did you find the information on this page useful?

Characters remaining:

Feedback Message