L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents

6.3. Multiple Reconfiguration Profiles

You should enable multiple configurations or profiles in the same Native PHY, Transmit PLL IP core, or both Parameter Editors for performing dynamic reconfiguration. This allows the IP Parameter Editor to create, store, and analyze the parameter settings for multiple configurations or profiles.
Note: fPLL in Core mode does not support the dynamic reconfiguration feature.

When you enable the multiple reconfiguration profiles feature, the Native PHY, Transmit PLL, or both IP cores can generate configuration files for all the profiles in the format desired (SystemVerilog package, MIF, or C header file). The configuration files are located in the <IP instance name>/reconfig/ subfolder of the IP instance with the configuration profile index added to the filename. For example, the configuration file for Profile 0 is stored as <filename_CFG0.sv>. The Intel® Quartus® Prime Timing Analyzer includes the necessary timing paths for all the configurations based on initial and target profiles. You can also generate reduced configuration files that contain only the attributes that differ between the multiple configured profiles. You can create up to eight reconfiguration profiles (Profile 0 to Profile 7) at a time for each instance of the Native PHY/Transmit PLL IP core.

Note: The addresses and bit settings of EMIB for a chosen configuration are available in the configuration files generated by the Native PHY IP.

The configuration files generated by Native PHY IP also include PMA analog settings specified in the Analog PMA settings tab of the Native PHY IP Parameter Editor. The analog settings selected in the Native PHY IP Parameter Editor are used to include these settings and their dependent settings in the selected configuration files.

Refer to "Steps to Perform Dynamic Reconfiguration" for a complete list of steps to perform dynamic reconfiguration using the IP guided reconfiguration flow with multiple reconfiguration profiles enabled.

To perform a PMA reconfiguration such as TX PLL switching, CGB divider switching, or reference clock switching, you must use the flow described in "Steps to Perform Dynamic Reconfiguration".

You can use the multiple reconfiguration profiles feature without using the embedded reconfiguration streamer feature. When using the multiple reconfiguration profiles feature by itself, you must write the user logic to reconfigure all the entries that are different between the profiles while moving from one profile to another.

Note: You must ensure that none of the profiles in the Native PHY IP and Transmit PLL IP Core Parameter Editor gives error messages, or the IP generation fails. The Native PHY IP core and Transmit PLL IP core only validates the current active profile dynamically. For example, if you store a profile with error messages in the Native PHY IP or Transmit PLL IP Core Parameter Editor and load another profile without any error messages, the error messages disappear in the IP. You are allowed to generate the IP, but the generation fails. For timing closure for each profile, please refer to "Timing Closure Recommendations" section.