188.8.131.52. Implementing Multi-Channel x24 Non-Bonded Configuration
Using the x24 non-bonded configuration reduces the number of PLL resources and the reference clock sources used.
- You can use either the ATX PLL or fPLL for multi-channel x24 non-bonded configuration.
Refer to Instantiating the ATX PLL IP Core or Instantiating the fPLL IP Core for detailed steps.
- Only the ATX PLL or fPLL can be used for this example, because the CMU PLL cannot drive the master CGB.
- Configure the PLL IP core using the IP Parameter Editor. Enable Include Master Clock Generation Block .
- Configure the Native PHY IP core using the IP Parameter Editor
- Set the Native PHY IP core TX Channel bonding mode to Non-Bonded .
- Set the number of channels as per your design requirement. In this example, the number of channels is set to 10.
- Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
- In this case, the PLL IP core has mcgb_serial_clk output port. This represents the x24 clock line.
- The Native PHY IP core has 10 (for this example) tx_serial_clk input ports. Each port corresponds to the input of the local CGB of the transceiver channel.
- As shown in the figure above, connect the mcgb_serial_clk output port of the PLL IP core to the 10 tx_serial_clk input ports of the Native PHY IP core.
- Leave the PLL IP’s tx_serial_clk output port unconnected.
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