7.5. User Recalibration
Power up calibration automatically calibrates all PLLs and transceiver channels used in your application. User recalibration is required if the following conditions are met:
- During device power up, OSC_CLK_1 is asserted and running stable, but the transceiver reference clock remains de-asserted until after the power up process is complete.
- During device power up, OSC_CLK_1 and the transceiver reference clock are asserted and running stable. When the device power up process is complete, the transceiver reference clock changes frequency. When this happens, either the transceiver reference clock could become unstable or your application requires a different transceiver reference clock during normal operation, which could cause a data rate change.
- After device power up in normal operation, you reconfigure the transceiver data rate.
- If you use the CDR CMU as a TX PLL, you must recalibrate the PMA TX of the channel which uses the CDR CMU as a TX PLL.
- If you recalibrate the TX PLL due to an unstable reference clock during power up calibration, you must recalibrate the PMA TX after TX PLL recalibration.
- If the TX PLL and CDR share the same reference clock which is unstable during power up calibration, you must recalibrate the TX PLL, PMA TX and PMA RX. The PMA RX calibration includes CDR calibration.
- Recalibrate the fPLL if the fPLL is connected as a second PLL (downstream cascaded PLL). This is important especially if the first PLL output clock is not stable.
You must also reset the transceivers after performing a user recalibration. For example, if you perform a data rate auto-negotiation that involves PLL reconfiguration and PLL and channel interface switching, then you must reset the transceivers.
The proper reset sequence is required after calibration. Intel recommends you use the Intel® Stratix® 10 Transceiver Reset Controller IP which has tx_cal_busy and rx_cal_busy inputs and follow Intel's recommended reset sequence. You need to connect tx_cal_busy and rx_cal_busy from the Native PHY IP core outputs to the reset controller inputs in your design. Reset upon calibration is automatically processed when you perform user recalibration.
You can initiate the recalibration process by writing to the specific recalibration registers. You must enable capability registers when generating the Native PHY IP or PLL IP cores to have access to the 0x480 or 0x481 registers.
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