L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.15. Standard PCS Ports

Figure 29. Transceiver Channel using the Standard PCS PortsStandard PCS ports appear if you have selected either one of the transceiver configuration modes that use the Standard PCS .

In the following tables, the variables represent these parameters:

  • <n>—The number of lanes
  • <w>—The width of the interface
  • <d>—The serialization factor
  • <s>— The symbol size
  • <p>—The number of PLLs
Table 73.  Rate Match FIFO
Name Direction Clock Domain Description
rx_std_rmfifo_full[<n>-1:0]

Output

Asynchronous

SSR17

Rate match FIFO full flag. When asserted the rate match FIFO is full. You must synchronize this signal. This port is only used for GigE mode.

rx_std_rmfifo_empty[<n>-1:0]

Output

Asynchronous

SSR17

Rate match FIFO empty flag. When asserted, match FIFO is empty. You must synchronize this signal. This port is only used for GigE mode.

rx_rmfifostatus[<2*n>-1:0]

Output

Asynchronous

Indicates FIFO status. The following encodings are defined:

  • 2'b00: Normal operation
  • 2'b01: Deletion, rx_std_rmfifo_full = 1
  • 2'b10: Insertion, rx_std_rmfifo_empty = 1
  • 2'b11: Full.

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

Table 74.  8B/10B Encoder and Decoder
Name Direction Clock Domain Description
tx_datak

Input

tx_clkout

tx_datak is exposed if 8B/10B enabled and simplified data interface is set.When 1, indicates that the 8B/10B encoded word of tx_parallel_data is control. When 0, indicates that the 8B/10B encoded word of tx_parallel_data is data.

For most configurations with simplified data interface disabled, tx_datak corresponds to tx_parallel_data[8].

For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Serializer is enabled, tx_datak corresponds to tx_parallel_data[8] and tx_parallel_data[19].

For PMA width of 20-bit with double rate transfer mode is disabled and Byte Serializer enabled, tx_datak corresponds to tx_parallel_data[8], tx_parallel_data[19], tx_parallel_data[48], and tx_parallel_data[59].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus[1:0] corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

tx_forcedisp[<n>(<w>/<s>-1:0]

Input

Asynchronous

tx_forcedisp is only exposed if 8B/10B, 8B/10B disparity control, and simplified data interface has been enabled. This signal allows you to force the disparity of the 8B/10B encoder. When "1", forces the disparity of the output data to the value driven on tx_dispval. When "0", the current running disparity continues.

For most configurations with simplified data interface disabled, tx_forcedisp corresponds to tx_parallel_data[9].

For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Serializer is enabled, tx_forcedisp corresponds to tx_parallel_data[9] and tx_parallel_data[20].

For PMA width of 20-bit with double rate transfer mode is disabled and Byte Serializer enabled, tx_forcedisp corresponds to tx_parallel_data[9], tx_parallel_data[20], tx_parallel_data[49], and tx_parallel_data[60].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

tx_dispval[<n>(<w>/<s>-1:0]

Input

Asynchronous

tx_dispval is exposed if 8B/10B, 8B/10B disparity control, and simplified data interface has been enabled. Specifies the disparity of the data. When 0, indicates positive disparity, and when 1, indicates negative disparity.

For most configurations with simplified data interface disabled, tx_dispval corresponds to tx_parallel_data[10].

For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Serializer is enabled, tx_forcedisp corresponds to tx_parallel_data[10] and tx_parallel_data[21].

For PMA width of 20-bit with double rate transfer mode is disabled and Byte Serializer enabled, tx_dispval corresponds to tx_parallel_data[10], tx_parallel_data[21], tx_parallel_data[50], and tx_parallel_data[61].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

rx_datak[<n><w>/<s>-1:0]

Output

rx_clkout

rx_datak is exposed if 8B/10B is enabled and simplified data interface is set. When 1, indicates that the 8B/10B decoded word of rx_parallel_data is control. When 0, indicates that the 8B/10B decoded word of rx_parallel_data is data.

For most configurations with simplified data interface disabled, rx_datak corresponds to rx_parallel_data[8].

For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Serializer is enabled, rx_datak corresponds to rx_parallel_data[8] and rx_parallel_data[24].

For PMA width of 20-bit with double rate transfer mode is disabled and Byte Serializer enabled, rx_datak corresponds to rx_parallel_data[8], rx_parallel_data[24], rx_parallel_data[48], and tx_parallel_data[64].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

rx_errdetect[<n><w>/<s>-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

When asserted, indicates a code group violation detected on the received code group. Used along with rx_disperr signal to differentiate between code group violation and disparity errors. The following encodings are defined for rx_errdetect/rx_disperr:

  • 2'b00: no error
  • 2'b10: code group violation
  • 2'b11: disparity error.

    For most configurations with simplified data interface disabled, rx_errdetect corresponds to rx_parallel_data[9].

    For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_errdetect corresponds to rx_parallel_data[9] and rx_parallel_data[25].

    For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_errdetect corresponds to rx_parallel_data[9], rx_parallel_data[25], rx_parallel_data[49], and rx_parallel_data[65].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

rx_disperr[<n><w>/<s>-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

When asserted, indicates a disparity error on the received code group.

For most configurations with simplified data interface disabled, rx_disperr corresponds to rx_parallel_data[11].

For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_disperr corresponds to rx_parallel_data[11] and rx_parallel_data[27].

For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_disperr corresponds to rx_parallel_data[11], rx_parallel_data[27], rx_parallel_data[51], and rx_parallel_data[67].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

rx_runningdisp[<n><w>/<s>-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

When high, indicates that rx_parallel_data was received with negative disparity. When low, indicates that rx_parallel_data was received with positive disparity.

For most configurations with simplified data interface disabled, rx_runningdisp corresponds to rx_parallel_data[15].

For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_runningdisp corresponds to rx_parallel_data[15] and rx_parallel_data[31].

For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_runningdisp corresponds to rx_parallel_data[15], rx_parallel_data[31], rx_parallel_data[55], and rx_parallel_data[71].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

rx_patterndetect[<n><w>/<s>-1:0] Output Asynchronous When asserted, indicates that the programmed word alignment pattern has been detected in the current word boundary.

Refer to "Word Alignment Using the Standard PCS" section for more details.

For most configurations with simplified data interface disabled, rx_patterndetect corresponds to rx_parallel_data[12].

For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_patterndetect corresponds to rx_parallel_data[12] and rx_parallel_data[28].

For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_patterndetect corresponds to rx_parallel_data[12], rx_parallel_data[28], rx_parallel_data[52], and rx_parallel_data[68].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

rx_syncstatus[<n><w>/<s>-1:0] Output Asynchronous When asserted, indicates that the conditions required for synchronization are being met.

Refer to "Word Alignment Using the Standard PCS" section for more details.

rx_syncstatus is bus dependent on the width of the parallel data. For example, when the parallel data width is 32 bits, then rx_syncstatus is a 4 bit bus. The final expected value is 1'hf, indicating the control character is identified at the correct location in the 32 bit parallel word.

For most configurations with simplified data interface disabled, rx_syncstatus corresponds to rx_parallel_data[10].

For PMA width of 10-bit with double rate transfer mode disabled or PMA width of 20-bit with double rate transfer mode enabled and the Byte Deserializer is enabled, rx_syncstatus corresponds to rx_parallel_data[10] and rx_parallel_data[26].

For PMA width of 20-bit with double rate transfer mode is disabled and Byte Deserializer enabled, rx_syncstatus corresponds to rx_parallel_data[10], rx_parallel_data[26], rx_parallel_data[50], and rx_parallel_data[66].

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

Table 75.  Word Aligner and Bitslip
Name Direction Clock Domain Description
tx_std_bitslipboundarysel[5 <n>-1:0] Input

Asynchronous

SSR17

Bitslip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip.

rx_std_bitslipboundarysel[5 <n>-1:0] Output

Synchronous to

rx_clkout

This port is used in deterministic latency word aligner mode. It reports the number of bits that the RX block slipped to achieve deterministic latency.

rx_std_wa_patternalign[<n>-1:0] Input

Asynchronous

SSR17

This port is enabled when you place the word aligner in manual mode. In manual mode, you align words by asserting rx_std_wa_patternalign. When the PCS-PMA Interface width is 10 bits, rx_std_wa_patternalign is level sensitive. For all the other PCS-PMA Interface widths, rx_std_wa_patternalign is positive edge sensitive.

You can use this port only when the word aligner is configured in manual or deterministic latency mode.

When the word aligner is in manual mode, and the PCS-PMA interface width is 10 bits, this is a level sensitive signal. In this case, the word aligner monitors the input data for the word alignment pattern, and updates the word boundary when it finds the alignment pattern.

For all other PCS-PMA interface widths, this signal is edge sensitive.This signal is internally synchronized inside the PCS using the PCS parallel clock and should be asserted for at least 2 clock cycles to allow synchronization.

rx_std_wa_a1a2size[<n>-1:0] Input

Asynchronous

SSR17

Used for the SONET protocol. Assert when the A1 and A2 framing bytes must be detected. A1 and A2 are SONET framing alignment overhead bytes and are only used when the PMA data width is 8 or 16 bits.

The 2 alignment markers valid status is captured in the 2 bit of rx_std_wa_ala2size signal. When both the markers are matched, then the value of the signal is 2'b11.

If simplified data interface is disabled, rx_rmfifostatus is a part of rx_parallel_data. For most configurations, rx_rmfifostatus corresponds to rx_parallel_data[14:13]. Refer to section Transceiver PHY PCS-to-Core Interface Reference Port Mapping to identify the port mappings to rx_parallel_data for your specific transceiver configurations.

rx_bitslip[<n>-1:0] Input

Asynchronous

SSR17

Used when word aligner mode is bitslip mode. When the Word Aligner is in either Manual (FPGA Fabric width controlled), Synchronous State Machine or Deterministic Latency ,the rx_bitslip signal is not valid and should be tied to 0. For every rising edge of the rx_std_bitslip signal, the word boundary is shifted by 1 bit. Each bitslip removes the earliest received bit from the received data.

Table 76.  Bit Reversal and Polarity Inversion
Name Direction Clock Domain Description
rx_std_byterev_ena[<n>-1:0]

Input

Asynchronous

SSR17

This control signal is available when the PMA width is 16 or 20 bits. When asserted, enables byte reversal on the RX interface. Use this when the MSB and LSB byte order of data packet from transmitter is inverted order than receiver.

rx_std_bitrev_ena[<n>-1:0]

Input

Asynchronous

SSR17

When asserted, enables bit reversal on the RX interface. Bit order may be reversed if external transmission circuitry transmits the most significant bit first. When enabled, the receiver receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner.

tx_polinv[<n>-1:0]

Input

Asynchronous

SSR17

When asserted, the TX polarity bit is inverted. Only active when TX bit polarity inversion is enabled.

rx_polinv[<n>-1:0]

Input

Asynchronous

SSR17

When asserted, the RX polarity bit is inverted. Only active when RX bit polarity inversion is enabled.

17 For a detailed description of FSR and SSR signals, please go to the Asynchronous Data Transfer section.

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