L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.2.1. Dedicated Reference Clock Pins

To minimize the jitter, the advanced transmit (ATX) PLL and the fractional PLL (fPLL) can source the input reference clock directly from the reference clock buffer without passing through the reference clock network. The input reference clock is also fed into the reference clock network. It can also drive the core fabric.
Note: The reference clock pins use thick oxide and are thus safe from damage due to hot swapping.

Set the following assignments to the dedicated reference clock pins through the Assignment Editor of the Intel® Quartus® Prime Pro Edition software. Since the reference clock is a direct input to the Native PHY IP core and not an analog parameter you cannot set it through the GUI.

Use the XCVR_S10_REFCLK_TERM_TRISTATE QSF assignment to set the refclk tristate termination setting. All other assignments like INPUT_TERMINATION DIFFERENTIAL, XCVR_REFCLK_PIN_TERMINATION AC_COUPLING, XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_EXTERNAL_RESISTOR, and XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_INTERNAL_100_OHMS are for older device families and will be ignored when used for Intel® Stratix® 10 devices.

Figure 150. Dedicated Reference Clock PinsThere are two dedicated reference clock (refclk) pins available in each transceiver bank. The bottom refclk pin feeds the bottom ATX PLL and fPLL. The top refclk pin feeds the top ATX PLL, fPLL, and CMU PLL via the reference clock network. The dedicated reference clock pins can also drive the reference clock network and the core fabric.

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