L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents Gen3 Features

The following subsections describes the Intel® Stratix® 10 transceiver block support for PIPE Gen3 features.

The PCS supports the PIPE 3.0 base specification. The 32-bit wide PIPE 3.0-based interface controls PHY functions such as transmission of electrical idle, receiver detection, and speed negotiation and control.

Auto-Speed Negotiation (ASN)

PIPE Gen3 mode enables ASN between Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) signaling datarates. The signaling rate switch is accomplished through frequency scaling and configuration of the PMA and PCS blocks using a fixed 32-bit wide PIPE 3.0-based interface.

The PMA switches clocks between Gen1, Gen2, and Gen3 datarates. For a non bonded x1 channel, an ASN module facilitates speed negotiation in that channel. For bonded x2, x4, x8 and x16 channels, the ASN module selects the master channel to control the rate switch. The master channel distributes the speed change request to the other PMA and PCS channels.

The PCIe Gen3 speed negotiation process is initiated when Hard IP or the FPGA fabric requests a rate change. The ASN then places the PCS in reset, and dynamically shuts down the clock paths to disengage the current active state PCS (either Standard PCS or Gen3 PCS). If a switch to or from Gen3 is requested, the ASN automatically selects the correct PCS clock paths and datapath selection in the multiplexers. The ASN block then sends a request to the PMA block to switch the datarate, and waits for a rate change done signal for confirmation. When the PMA completes the rate change and sends confirmation to the ASN block, the ASN enables the clock paths to engage the new PCS block and releases the PCS reset. Assertion of the pipe_phy_status signal by the ASN block indicates the successful completion of this process.

Note: In Native PHY IP core - PIPE configuration, you must set pipe_rate[1:0]to initiate the transceiver datarate switch sequence.

Rate Switch

This section provides an overview of auto rate change between PIPE Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) modes.
In Intel® Stratix® 10 devices, there is one ASN block common to the Standard PCS and Gen3 PCS, located in the PMA-PCS interface that handles all PIPE speed changes. The PIPE interface clock rate is adjusted to match the data throughput when a rate switch is requested.
PIPE Gen3 32 bit PCS Clock Rates
PCIe Gen3 Capability Mode Enabled Gen1 Gen2 Gen3
Lane datarate 2.5 Gbps 5 Gbps 8 Gbps
PCS clock frequency 250 MHz 500 MHz 250 MHz
FPGA fabric IP clock frequency 62.5 MHz 125 MHz 250 MHz
PIPE interface width 32-bit 32-bit 32-bit
pipe_rate [1:0] 2'b00 2'b01 2'b10
Rate Switch ChangeThe block-level diagram below shows a high level connectivity between ASN and Standard PCS and Gen3 PCS.

The sequence of speed change between Gen1, Gen2, and Gen3 occurs as follows:

  1. The PHY-MAC layer implemented in FPGA fabric requests a rate change through pipe_rate[1:0].
  2. The ASN block waits for the TX FIFO to flush out data. Then the ASN block asserts the PCS reset.
  3. The ASN asserts the clock shutdown signal to the Standard PCS and Gen3 PCS to dynamically shut down the clock.
  4. When the rate changes to or from the Gen3 speed, the ASN asserts the clock and data multiplexer selection signals.
  5. The ASN uses a pipe_sw[1:0] output signal to send a rate change request to the PMA.
  6. The ASN continuously monitors the pipe_sw_done[1:0] input signal from the PMA.
  7. After the ASN receives the pipe_sw_done[1:0] signal, it deasserts the clock shut down signals to release the clock.
  8. The ASN deasserts the PCS reset.
  9. The ASN sends the speed change completion to the PHY-MAC interface. This is done through the pipe_phy_status signal to PHY-MAC interface.
Speed Change Sequence

Gen3 Transmitter Electrical Idle Generation

In the PIPE 3.0-based interface, you can place the transmitter in electrical idle during low power states. Before the transmitter enters electrical idle, you must send the Electrical Idle Ordered Set, consisting of 16 symbols with value 0x66. During electrical idle, the transmitter differential and common mode voltage levels are based on the PCIe Base Specification 3.0.

Gen3 Clock Compensation

Enable this mode from the Native PHY IP core when using the Gen3 PIPE transceiver configuration rule.

To accommodate PCIe protocol requirements and to compensate for clock frequency differences of up to ±300 ppm between source and termination equipment, receiver channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP characters (32 bits) to keep the FIFO from becoming empty or full. If the rate match FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is nearly empty, the FIFO inserts a SKP character at the start of the next available SKP ordered set. The pipe_rx_status [2:0] signal indicates FIFO full, empty, insertion and deletion.
Note: Refer to Gen1 and Gen2 Clock Compensation for waveforms.

Gen3 Power State Management

The PCIe base specification defines low power states for PHY layer devices to minimize power consumption. The Gen3 PCS does not implement these power saving measures, except when placing the transmitter driver in electrical idle in the low power state. In the P2 low power state, the transceivers do not disable the PIPE block clock.

Figure 100. P1 to P0 TransitionThe figure below shows the transition from P1 to P0 with completion provided by pipe_phy_status.

CDR Control

The CDR control block performs the following functions:
  • Controls the PMA CDR to obtain bit and symbol alignment
  • Controls the PMA CDR to deskew within the allocated time
  • Generates status signals for other PCS blocks
The PCIe base specification requires that the receiver L0s power state exit time be a maximum of 4 ms for Gen1, 2 ms for Gen2, and 4 ms for Gen3 signaling rates. The transceivers have an improved CDR control block to accommodate fast lock times. Fast lock times are necessary for the CDR to relock to the new multiplier/divider settings when entering or exiting Gen3 speeds.


As per the PIPE 3.0 specification, for every 128 bits that are moved across the Gen3 PCS, the PHY must transmit 130 bits of data. Intel uses the pipe_tx_data_valid signal every 16 blocks of data to transmit the built-up backlog of 32 bits of data.

The 130-bit block is received as follows in the 32-bit data path: 34 (32+2-bit sync header), 32, 32, 32. During the first cycle, the gearbox converts the 34-bit input data to 32-bit data. During the next three clock cycles, the gearbox merges bits from adjacent cycles. For the gearbox to work correctly, a gap must be provided in the data for every 16 shifts because each shift contains two extra bits for converting the initial 34 bits to 32 bits in the gearbox. After 16 shifts, the gearbox has an extra 32 bits of data that are transmitted out. This requires a gap in the input data stream, which is achieved by driving pipe_tx_data_valid low for one cycle after every 16 blocks of data.

Figure 101. Gen3 Data Transmission