L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.3.2. Embedded Reconfiguration Streamer

You can optionally enable the embedded reconfiguration streamer in the Native PHY, Transmit PLL, or both IP cores to automate the reconfiguration operation. The embedded reconfiguration streamer is a feature block that can perform Avalon® memory-mapped interface transactions to access channel/Transmit PLL configuration registers in the transceiver. When you enable the embedded streamer, the Native PHY/Transmit PLL IP cores embed HDL code for reconfiguration profile storage and reconfiguration control logic in the IP files.

For the Transmit PLL IP, you can initiate the reconfiguration operation by writing to the control registers of the PLL using reconfiguration interface. Control and status signals of the streamer block are memory mapped in the PLL’s soft control and status registers.

For the Native PHY IP, you can initiate the reconfiguration operation by writing to the control registers of the channel using reconfiguration interface. Control and status signals of the streamer block are memory mapped in the PHY’s soft control and status registers. These embedded reconfiguration control and status registers are replicated for each channel.
Note: You cannot merge reconfiguration interfaces across multiple IP cores when the embedded reconfiguration streamer is enabled. Refer to "Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks" section for more details.

For example, if the Native PHY IP core has four channels—logical channel 0 to logical channel 3—and you want to reconfigure logical channel 3 using the embedded reconfiguration streamer, you must write to the control register of logical channel 3 using the reconfiguration interface with the appropriate bit settings.

Note: The addresses and bit settings of EMIB for a chosen configuration are available in the configuration files generated by the Native PHY IP.

The configuration files generated by Native PHY IP also include the Analog PMA settings tab of the Native PHY IP Parameter Editor. The analog settings selected in the Native PHY IP Parameter Editor are used to include these settings and their dependent settings in the selected configuration files.

Refer to "Steps to Perform Dynamic Reconfiguration" for a complete list of steps to perform dynamic reconfiguration using the IP guided reconfiguration flow with embedded streamer enabled. To perform a PMA reconfiguration such as TX PLL switching, CGB divider switching, or reference clock switching, use the reconfiguration flow for special cases described in "Steps to Perform Dynamic Reconfiguration".

Refer to Logical View of the L-Tile/H-Tile Transceiver Registers for more details on Embedded reconfiguration streamer registers and bit settings.

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