L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.5.4. Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP Resource Utilization

This section describes the estimated device resource utilization for two configurations of the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. The exact resource count varies by the version of the Intel® Quartus® Prime Pro Edition software, as well as by optimization options.
Table 147.   Reset Controller Resource Utilization

Configuration

Combination ALUTs

Logic Registers

Single transceiver channel

approximately 35

approximately 45

Four transceiver channels, shared TX reset, separate RX resets

approximately 100

approximately 150

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