L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents
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A.6. Logical View Register Map of the L-Tile/H-Tile Transceiver Registers Revision History

Document Version Changes
  • Added new Transmitter PLL Switching Register Map table with transmitter PLL switching register map information.
  • Updated Channel Logical Register Map with Start PMA DFE adaptation auto feature.
  • Updated the table title from RX PMA to RX Bandwidth Selection.
  • Added the following tables:
    • Updating ATX PLL Fractional Multiply Factor (K) Value
    • TX Termination
    • RX Termination
2020.10.05 Made the following change:
  • Clarified that the square wave generator is available in 64-bit PCS-PMA data widths only.
2018.10.05 Made the following change:
  • Added the Background calibration feature to the "CDR/CMU and PMA Calibration" section.
2018.08.27 Made the following change:
  • Corrected the binary encoding for TX Output Swing level in the "VOD" section.
2018.07.12 Made the following change:
  • Updated the description of address 0x100[3] in the "CDR/CMU and PMA Calibration" section.
2018.07.06 Made the following changes:
  • Clarified the encodings for slew rate in the "Slew Rate" section.
  • Added the "Setting RX PMA Adaptation Modes" section.
  • Changed the encodings in the "Static Polarity Inversion" section.
2018.04.16 Made the following change:
  • Remove the "Setting RX PMA Adaptation Modes" section.
2017.08.11 Made the following changes:
  • Added new registers to the "Setting RX PMA Adaptation Modes" section.
  • Changed the instructions in STEP A and STEP C in the "Adaptation Control - Start" section.
2017.06.06 Initial release.