L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

7.1. Reconfiguration Interface and Arbitration with PreSICE (Precision Signal Integrity Calibration Engine)

In Intel® Stratix® 10 devices, calibration is performed using the PreSICE. The PreSICE includes an Avalon® memory-mapped interface to access the transceiver channel and PLL programmable registers. This Avalon® memory-mapped interface includes a communication mechanism that enables you to request specific calibration sequences from the calibration controller.

The PreSICE Avalon® memory-mapped interface and user Avalon® memory-mapped interface reconfiguration both share an internal configuration bus. This bus is arbitrated to gain access to the transceiver channel and PLL programmable registers, and the calibration registers.

There are two ways to check which one has access to the internal configuration bus:

  • Use the dynamic reconfiguration interface reconfig_waitrequest
  • Use capability registers

The Native PHY IP core and PLL default setting is to use reconfig_waitrequest. When PreSICE controls the internal configuration bus, the reconfig_waitrequest from the internal configuration bus is high. When user access is granted, the reconfig_waitrequest signal from the internal configuration bus goes low.

To use the capability registers to check bus arbitration:

  1. Select Enable dynamic reconfiguration from the Dynamic Reconfiguration tab in the PHY and PLL GUI.
  2. Select both the Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE and Enable control and status registers options.
Reading the capability register 0x481[2] identifies what is controlling the channel access. Reading the capability register 0x480[2] identifies what is controlling the ATX and fPLL access.
Note: When Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE and Enable control and status registers are enabled, reconfig_waitrequest is not asserted high when PreSICE controls the internal configuration bus.

To return the internal configuration bus to PreSICE:

  • Write 0x1 to offset address 0x0[0] if any calibration bit is enabled from offset address 0x100.
  • Write 0x3 to offset address 0x0[1:0] if no calibration bit has been enabled from offset address 0x100.

To check if the calibration process is running, do one of the following:

  • Monitor the pll_cal_busy, tx_cal_busy, and rx_cal_busy Native PHY output signals.
  • Read the tx/rx/pll_cal_busy signal status from the capability registers.

The tx/rx/pll_cal_busy signals remain asserted as long as the calibration process is running. To check whether or not calibration is complete, you can read the capability registers or check the tx/rx/pll_cal_busy signals. The PMA tx_cal_busy and rx_cal_busy are from the same internal node, which cannot be separated from the hardware. The capability register 0x481[5:4] can enable or disable tx_cal_busy or rx_cal_busy individually. Using capability register 0x481[5:4] to isolate tx_cal_busy and rx_cal_busy is not supported in simplex TX and RX merging into a signal physical channel. See details in Capability Registers.

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