The Interlaken interface is supported with 1 to 24 lanes running at datarates up to 17.4 Gbps per lane on Intel® Stratix® 10 devices. Interlaken is implemented using the Enhanced PCS.
Intel® Stratix® 10 devices provide three preset variations for Interlaken in the Intel® Stratix® 10 Transceiver Native PHY IP Parameter Editor:
- Interlaken 10x12.5 Gbps
- Interlaken 1x6.25 Gbps
- Interlaken 6x10.3 Gbps
Depending on the line rate, the Enhanced PCS can use a PMA to PCS interface width of 32, 40, or 64 bits.
The Native PHY IP core does not support double rate transfer option when configured in Interlaken.