L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

1.3.5.2. Input Reference Clock Sources

  • Eight dedicated reference clocks available per transceiver tile
    • Two reference clocks per transceiver bank
    • You must route multiple copies of reference clocks on the PCB to span beyond a transceiver tile
  • Reference clock network
    • Reference clock network does not span beyond the transceiver tile
    • There are two regulated reference clock networks for better performance per tile that any reference clock pin can access
  • You can use unused receiver pins as additional reference clocks
Note: Unused receiver pins used as reference clocks can only be used within the same tile.
Figure 18. Reference Clock Network

For the best jitter performance, place the reference clock as close as possible to the transmit PLL. Use the reference clock in the same triplet of the bank as the transmit PLL.

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