L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.9.1.1. x6/x24 Bonding

In x6/x24 bonding mode, a single transmit PLL is used to drive multiple channels.

The steps below explain the x6/24 bonding process:

  1. The ATX PLL or the fPLL generates a high speed serial clock.
  2. The PLL drives the high speed serial clock to the master CGB via the x1 clock network.
  3. The master CGB drives the high speed serial and the low speed parallel clock into the x6 clock network.
  4. The x6 clock network feeds the TX clock multiplexer for the transceiver channels within the same transceiver bank. The local CGB in each transceiver channel is bypassed.
  5. To drive the channels in adjacent transceiver banks, the x6 clock network drives the x24 clock network. The x24 clock network feeds the TX clock multiplexer for the transceiver channels in these adjacent transceiver banks.
Note: The x24 clock lines are only allowed to traverse between contiguous banks operating at the same VCCR_GXB/VCCT_GXB voltages. The x24 clock lines crossing boundaries of banks operating at different voltages is not allowed.

For more information about the transceiver power connection guidelines, refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines.

Did you find the information on this page useful?

Characters remaining:

Feedback Message