L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.10. Dynamic Reconfiguration Parameters

Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without powering down the device.

Each transceiver channel and PLL includes an Avalon® memory-mapped interface slave for reconfiguration. This interface provides direct access to the programmable address space of each channel and PLL. Because each channel and PLL includes a dedicated Avalon® memory-mapped interface slave, you can dynamically modify channels either concurrently or sequentially. If your system does not require concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.

You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths.

To enable Intel® Stratix® 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:

  • Enable dynamic reconfiguration
  • Enable Native PHY Debug Master Endpoint
  • Enable capability registers
  • Enable control and status registers
  • Enable PRBS (Pseudo Random Binary Sequence) soft accumulators
Table 45.  Dynamic Reconfiguration
Parameter Value Description
Enable dynamic reconfiguration On/Off When you turn on this option, the dynamic reconfiguration interface is enabled.
Enable Native PHY Debug Master Endpoint On/Off When you turn on this option, the Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® memory-mapped interface slave for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel.
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE On/Off When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the Enable control and status registers feature under Optional Reconfiguration Logic be enabled.
Share reconfiguration interface On/Off When you turn on this option, the Transceiver Native PHY IP presents a single Avalon® memory-mapped interface slave for dynamic reconfiguration for all channels. In this configuration, the upper [n-1:11] address bits of the reconfiguration address bus specify the channel. The channel numbers are binary encoded. Address bits [10:0] provide the register offset address within the reconfiguration space for a channel.
Enable rcfg_tx_digitalreset_release_ctrl port On/Off Enables the rcfg_tx_digitalreset_release_ctrl port that dynamically controls the TX PCS reset release sequence. This port usage is mandatory when reconfiguring to or from Enhanced PCS Configurations with TX PCS Gearbox ratios of either 32:67, 40:67, and 64:67.
Table 46.  Optional Reconfiguration Logic
Parameter Value Description
Enable capability registers On/Off Enables capability registers that provide high level information about the configuration of the transceiver channel.
Set user-defined IP identifier User-defined Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Enable control and status registers On/Off Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.
Enable PRBS (Pseudo Random Binary Sequence) soft accumulators On/Off Enables soft logic for performing PRBS bit and error accumulation when the hard PRBS generator and checker are used.
Table 47.  Configuration Files
Parameter Value Description
Configuration file prefix <prefix> Here, the file prefix to use for generated configuration files is specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files.
Generate SystemVerilog package file On/Off When you turn on this option, the Transceiver Native PHY IP generates a SystemVerilog package file, reconfig_parameters.sv. This file contains parameters defined with the attribute values required for reconfiguration.
Generate C header file On/Off When you turn on this option, the Transceiver Native PHY IP generates a C header file, reconfig_parameters.h. This file contains macros defined with the attribute values required for reconfiguration.
Generate MIF (Memory Initialize File) On/Off When you turn on this option, the Transceiver Native PHY IP generates a MIF, reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format.
Table 48.  Configuration Profiles
Parameter Value Description
Enable multiple reconfiguration profiles On/Off When enabled, you can use the GUI to store multiple configurations. This information is used by Quartus to include the necessary timing arcs for all configurations during timing driven compilation. The Native PHY generates reconfiguration files for all of the stored profiles. The Native PHY also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them. Among other things this checks that you have exposed the same ports for each configuration.8
Enable embedded reconfiguration streamer On/Off Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles. This is optional and increases logic utilization. The PHY includes all of the logic and data necessary to dynamically reconfigure between pre-configured profiles.
Generate reduced reconfiguration files On/Off When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles. The reconfiguration time decreases with the use of reduced .mif files.
Number of reconfiguration profiles 1-8 Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Store current configuration to profile 0-7 Selects which reconfiguration profile to store/load/clear/refresh, when clicking the relevant button for the selected profile.
Store configuration to selected profile - Clicking this button saves or stores the current Native PHY parameter settings to the profile specified by the Selected reconfiguration profile parameter.
Load configuration from selected profile - Clicking this button loads the current Native PHY with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter.
Clear selected profile - Clicking this button clears or erases the stored Native PHY parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY.
Clear all profiles - Clicking this button clears the Native PHY parameter settings for all the profiles.
Refresh selected profile - Clicking this button is equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the Native PHY parameter settings from stored profile specified by the Selected reconfiguration profile parameter and subsequently stores or saves the parameters back to the profile.
8 For more information on timing closure, refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter.

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