220.127.116.11.1. Gen1/Gen2 Features
In a PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks. The PIPE configuration is based on the PIPE 2.0 specification. If you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in the FPGA fabric.
Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
In a PIPE configuration, Native PHY IP core provides an input signal pipe_rate[1:0] that is functionally equivalent to the RATE signal specified in the PCIe specification. A change in value from 2'b00 to 2'b01 on this input signal pipe_rate[1:0] initiates a datarate switch from Gen1 to Gen2. A change in value from 2'b01 to 2'b00 on the input signal initiates a datarate switch from Gen2 to Gen1.
Transmitter Electrical Idle Generation
The PIPE interface block puts the transmitter buffer in an electrical idle state when the electrical idle input signal is asserted. During electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 datarates.
The PCIe specification requires the transmitter driver to be in electrical idle in certain power states. For more information about input signal levels required in different power states, refer to Power State Management.
Power State Management
To minimize power consumption, the physical layer device must support the following power states.
|P0||Normal operating state during which packet data is transferred on the PCIe link.|
|P0s, P1, and P2||The PHY-MAC layer directs the physical layer to transition into these low-power states.|
The PIPE interface provides a pipe_powerdown input port for each transceiver channel configured in a PIPE configuration.
The PCIe specification requires the physical layer device to implement power-saving measures when the P0 power state transitions to the low power states. Intel® Stratix® 10 transceivers do not implement these power-saving measures except for putting the transmitter buffer in electrical idle mode in the lower power states.
8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and Status State Machine (LTSSM) enters the Polling.Compliance substate. The Polling.Compliance substate assesses if the transmitter is electrically compliant with the PCIe voltage and timing specifications.
The PCIe specification requires the PHY to encode the receiver status on a 3-bit status signal pipe_rx_status[2:0]. This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the pipe_rx_status[2:0] signal to the FPGA fabric. The encoding of the status signals on the pipe_rx_status[2:0] signal conforms to the PCIe specification.
The PIPE interface block provides an input signal pipe_tx_detectrx_loopback for the receiver detect operation. The PCIe protocol requires this signal to be high during the Detect state of the LTSSM. When the pipe_tx_detectrx_loopback signal is asserted in the P1 power state, the PIPE interface block sends a command signal to the transmitter driver in that channel to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must always be in the electrical idle state. After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. The time constant of the step voltage on the trace increases if an active receiver that complies with the PCIe input impedance requirements is present at the far end. The receiver detect circuitry monitors this time constant to determine if a receiver is present.
The PIPE core provides a 1-bit PHY status signal pipe_phy_status and a 3-bit receiver status signal pipe_rx_status[2:0] to indicate whether a receiver is detected, as per the PIPE 2.0 specifications.
Gen1 and Gen2 Clock Compensation
PIPE 0 ppm
In compliance with the PIPE specification, Intel® Stratix® 10 receiver channels have a rate match FIFO to compensate for small clock frequency differences up to ±300 ppm between the upstream transmitter and the local receiver clocks.
Consider the following guidelines for PIPE clock compensation:
- Insert or delete one skip (SKP) symbol in an SKP ordered set.
Note: The SKP symbol is also represented as K28.0, and is used for compensating for different bit rates between two communicating ports.
- A minimum limit is imposed on the number of SKP symbols in SKP ordered set after deletion. A transmitted SKP ordered set is comprised of a single COM (K28.5) symbol followed by three SKP symbols. An ordered set may have an empty COM case after deletion.
- A maximum limit is imposed on the number of the SKP symbols in the SKP ordered set after insertion. An ordered set may have more than five symbols after insertion.
- For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP ordered set where insertion or deletion occurs.
- For FULL/EMPTY cases: The flag status appears where the character is inserted or deleted.
Note: The PIPE interface translates the value of the flag to the appropriate pipe_rx_status signal.
- The PIPE mode also has a “0 ppm” configuration option that you can use in synchronous systems. The Rate Match FIFO Block is not expected to do any clock compensation in this configuration, but latency will be minimized.
The PIPE mode also has a "0 ppm" configuration option that can be used in synchronous systems. The rate match FIFO is not expected to do any clock compensation in this configuration, but latency will be minimized.
PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available for PCIe Gen1, Gen2, and Gen3 datarates. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate match FIFO. The data is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the rx_parallel_data port. This loopback mode is based on PCIe specification 2.0. Intel® Stratix® 10 devices provide an input signal pipe_tx_detectrx_loopback to enable this loopback mode.