L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

A.5. Transmitter PLL Switching Register Map

Enables you to perform transmitter PLL switching.
Table 179.  Transmitter PLL Switching Register Map
Name Address Type Attribute Name Encoding
Clock Source Selection 0x111 [4:0]



6'b000000: Select LCPLL bottom

6'b000001: Select LCPLL top

6'b000010: Select fPLL bottom

6'b000011: Select fPLL top

6'b000100: Select CH1 TxPLL bottom

6'b000101: Select CH1 TxPLL top

6'b000110: Select same CH TxPLL

6'b000111: Select LCPLL high speed

6'b100000: Select LCPLL bottom

6'b100001: Select LCPLL top

6'b100010: Select fPLL bottom

6'b100011: Select fPLL top

6'b101000: FPLL_BOT_G2_LCPLL_BOT_G3

6'b101001: FPLL_BOT_G2_LCPLL_TOP_G3

6'b101010: FPLL_TOP_G2_LCPLL_BOT_G3 6'b101011: FPLL_TOP_G2_LCPLL_TOP_G3

6'b011000: Select from x6/xN TX clk mux

0x111 [7:5]



3'b000: Select XN up

3'b001: Select XN down

3'b010: Select X6 top

3'b011: Select X6 bottom

3'b100: Select local CGB
Note: Bits [6:5] are always set to 0 whenever bit [7] is set to 1.
Logical PLL Switch Look-Up 0x117 [3:0] read-only scratch0_x1_clock_src

These bits represent the logical PLL to physical mapping of PLLs

4'b0000: LCPLL Bot

4'b0001: LCPLL Top

4'b0010: fPLL Bot

4'b0011: fPLL Top

4'b0100: CH1 TxPLL Bot

4'b0101: CH1 TxPLL Top

4'b0110: Same CH TxPLL

4'b0111: LCPLL High Speed

4'b1000: HFCLK_XN_UP

4'b1001: HFCLK_XN_DN

4'b1010: HFCLK_X6_UP

4'b1011: HFCLK_X6_DN

4'b1111: Not Used

Note: The same mapping applies to all four registers.
0x117 [7:4] read-only scratch1_x1_clock_src
0x118 [3:0] read-only scratch2_x1_clock_src
0x118 [7:4] read-only scratch3_x1_clock_src