L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents
Give Feedback Interlaken Configuration Clocking and Bonding

The Interlaken PHY layer solution is scalable and has flexible datarates. You can implement a single lane link or bond up to 24 lanes together. You can choose a lane datarate up to 17.4 Gbps for GX devices. You can also choose between different reference clock frequencies, depending on the PLL used to clock the transceiver. Refer to the Intel® Stratix® 10 Device Datasheet for the minimum and maximum datarates that Intel® Stratix® 10 transceivers can support at different speed grades.

You can use an ATX PLL or fPLL to provide the clock for the transmit channel. An ATX PLL has better jitter performance compared to an fPLL. You can use a channel PLL as a CMU PLL to clock only the non-bonded Interlaken transmit channels. However, when the channel PLL is used as a CMU PLL, the channel can only be used as a transmitter channel.

For the multi-lane Interlaken interface, TX channels are usually bonded together to minimize the transmit skew between all bonded channels. Currently, the x24 bonding scheme is available to support a multi-lane Interlaken implementation. If the system tolerates higher channel-to-channel skew, you can choose to not bond the TX channels.

To implement bonded multi-channel Interlaken, all channels must be placed contiguously. The channels may all be placed in one bank (if not greater than six lanes) or they may span several banks.