L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

3.12. PLLs and Clock Networks Revision History

Document Version Changes
  • Updated Using the ATX PLL for GXT Channels section with corrected GXT clock output buffer parameter settings when used as a Primary PLL clock output buffer in the ATX PLL.
  • Updated ATX PLL IP Core - Ports table with a note for the pll_locked and pll_cal_busy ports.
  • Added note on updating the ATX PLL fractional multiply factor value via the reconfiguration interface of the ATX PLL in the Implementing PLL Cascading section.
2020.10.05 Made the following changes:
  • Clarified that the ATX PLL to fPLL spacing requirements rule applies to fPLLs in both transceiver mode and core mode.
  • Added this note to Implementing PLL Cascading and the pll_locked port definition: In ATX PLL to fPLL cascading mode, the pll_locked signal from the ATX PLL does not indicate the ATX PLL lock status. Refer to the downstream fPLL lock signal to indicate if both ATX and fPLL are locked.
2020.03.03 Made the following changes:
  • Updated the following figures to make it clear that rx_clkout is driven by CDR.
    • FPGA Fabric—Transceiver Interface Clocking (Standard PCS Example)
    • Transmitter Standard PCS and PMA Clocking
    • Transmitter Enhanced PCS and PMA Clocking
    • Receiver Standard PCS and PMA Clocking
    • Receiver Enhanced PCS and PMA Clocking
  • Clarified ATX PLL to fPLL Spacing Requirements.
  • Clarified that the reference clock for GXT channels must be located in the same triplet as the master ATX PLL.
  • Added this note, "Use the tx_clkout from the master channel as the source clock to drive the tx_coreclkin port for all other channels in the bonded interface."
  • Added HCLK Network.
  • In fPLL IP Core - Parameters, Settings, and Ports, clarified that fPLL in Core mode does not support the dynamic reconfiguration feature.
2019.03.22 Made the following change:
  • Added SATA GEN3 and HDMI to the Protocol Mode Range in the "fPLL IP Core - Configuration Options, Parameters, and Settings" table.
2019.01.23 Made the following changes:
  • Added a new requirement: The reference clock for GXT channels must be located in the same triplet as the master ATX PLL.
2018.10.05 Made the following changes:
  • Added GXT Clock buffers to the "Main and Adjacent ATX PLL IP Instances to Drive 6 GXT Channels" figure.
  • Removed the ATX PLL to ATX PLL spacing requirement from the "ATX PLL Spacing Requirements" table.
  • Updated the note in the "Input Reference Clock Sources" section.
  • Added a note to the "x6/x24 Bonding" section.
2018.10.04 Made the following changes:
  • Added "even if the VCCR_GXB and VCCT_GXB operating voltages of the banks in the tile are different" to Reference Clock Network.
  • Added the following to x24 Clock Lines:

    A maximum of 24 channels can be used in a single bonded or non-bonded x24 group. When the banks within a transceiver tile are powered at different voltages (for example, some banks are operating at 1.03 V while other banks are operating at 1.12 V), the x24 clock lines are only allowed to traverse between contiguous banks operating at the same VCCR_GXB and VCCT_GXB voltages. The x24 clock lines crossing boundaries of banks operating at different voltages is not allowed. See the Intel® Stratix® 10 Device Family Pin Connection Guidelines for a description of the transceiver power connection guidelines.

2018.07.06 Made the following changes:
  • Added a note to Using the ATX PLL for GXT Channels: An ATX PLL cannot be reconfigured from GX to GXT mode if the adjacent master CGB is being used.
  • Clarified reference clock and transmitter PLL location awareness in Reference Clock Network.
  • Added note to Clock Generation Block: If you are using a master CGB, do not configure the adjacent ATX PLL from a GX to a GXT mode.
  • For ATX PLL, fPLL, and CMU PLL IP Core - Parameters, Settings, and Ports, added "The ports related to reconfiguration are compliant with the Avalon® Specification. Refer to the Avalon® Specification for more details about these ports" to the Avalon® Specification link.
2018.03.16 Made the following changes:
  • Grayed the CGB blocks in "x6/x24 Bonding Mode —Internal Channel Connections" figure in "Implementing x6/x24 Bonding Mode" topic.
  • Updated "five fPLL instances" to 3 in the description of "PLL Instances" section.
  • Changed the description of the following parameters and ports in the "ATX PLL IP Core - Parameters, Settings, and Ports" section:
    • Enable mcgb_rst and mcgb_rst_stat ports
    • mcgb_rst
    • mcgb_rst_stat
  • Updated the data rates and configuration settings for PLL IP Cores and PHY IPs in "Mix and Match Example" section. Also updated from "four Transceiver Native PHY IP core instances and four 10GBASE-KR PHY IP instances" to 3 Native PHY IP core instances and 2 10GBASE-KR PHY IP instances.
  • Added "Lock Detector" block description for fPLL.
  • Note "All channels must be contiguously placed when using PMA/PCS bonding. Refer to the "Channel Bonding" section for more details." has been added in the "Implementing x6/x24 Bonding Mode" section.
  • Removed Clock Cascading Inputs for "Dedicated Reference Clock Pins" figure.
  • Updated term "TX phase compensation FIFO" to "TX PCS FIFO" in "Transmitter Data Path Interface Clocking" topic.
  • Added steps to implement a Single-Channel x1 Non-Bonded Configuration.
  • Added a note for PLL cascading "You may use this configuration to generate clock frequencies that cannot be generated by a single PLL. It is most commonly used for OTN/SDI applications."
  • Added a note "Each core clock network reference clock pin cannot drive fPLLs located on multiple L/H-Tiles".
  • Title of the figure changed from "FPGA Fabric—Transceiver Interface Clocking" to "FPGA Fabric—Transceiver Interface Clocking (Standard PCS Example)".
  • Added the sentence "For PCS Direct, the clocking architecture remains the same as Standard PCS" in "Transmitter Data Path Interface Clocking".
  • Changed the note in the "ATX PLL Spacing Requirements" section.
  • Re-organized "Dedicated Reference Clock Pins" and updated to current Intel® Quartus® Prime Pro Edition names and made QSF edits for the transceiver refclk.
  • Added "Leave the PLL IP’s tx_serial_clk output port unconnected" to "Implementing Multi-Channel x24 Non-Bonded Configuration."
  • Clarified the "Multi-Channel x1/x24 Non-Bonded Example" figure.
  • Changed L-Tile max data rate to 26.6 in "Transmit PLL Recommendation Based on Data Rates."
  • Clarified the "ATX PLL Spacing Requirements" table.
  • Changed GT to GXT in "ATX PLL GXT Clock Connection."
  • Added signal names to "PHY IP Core and PLL IP Core Connection for Multi-Channel x24 Non-Bonded Configuration."
  • Changed "adjacent" to "clock buffer" in "Using the ATX PLL for GXT Channels" and "GXT Implementation Usage Restrictions for ATX PLL GX & MCGB."
  • Updated "ATX PLL IP Parameter Details for Clock Buffer ATX PLL IP" and "ATX PLL IP Parameter Details for Main ATX PLL IP" figures.
  • Removed L-Tile from "GXT Clock Network."
  • Made rx_clkout and tx_clkout able to drive both Dedicated and Global Core Clock Networks for the "FPGA Fabric—Transceiver Interface Clocking (Standard PCS Example)" figure.
  • Changed support to fPLL to fPLL and ATX PLL to fPLL only for "PLL Cascading Clock Network."
2017.08.11 Made the following changes:
  • Added a note in "Dedicated Reference Clock Pins" topic stating "The reference clock pins use thick oxide and are thus safe from damage due to hot swapping".
  • Added a paragraph in the Reference Clock Network section : "You can only use the two high quality reference clock lines for one bottom and one top reference clock in a tile. There are fitter errors if you try to use both lines for two bottom reference clocks in a tile."
  • Added a note "For L-Tile, you can only have 4 GXT per tile, all in the same bank".
2017.06.06 Made the following changes:
  • Feedback compensation bonding is not supported.
  • Updated "ATX PLL Spacing Requirements" table.
  • Added a new section "GXT Implementation Usage Restrictions for ATX PLL GX & MCGB".
  • Updated "Reference Clock Network" section.
  • Added a new figure "Main and Adjacent ATX PLL IP Instances to Drive 6 GXT Channels".
  • Updated topic "Timing Closure Recommendations".
2017.03.08 Made the following changes:
  • Changed all the notes in the "Using the ATX PLL for GXT Channels" section.
2017.02.17 Made the following changes:
  • Updated the ATX PLL description to "ATX PLL only supports fractional mode".
  • Updated the L Counter description to "The division factor supported are 1 and 2".
  • Updated the Receiver Input Pins description to "Receiver input pins can be used as an input reference clock source to transceiver PLLs. However, they cannot be used to drive core fabric".
  • Added new section "ATX PLL Spacing Requirements".
  • Added new section "Using the ATX PLL for GXT Channels".
  • Added the following note in the relevant topics: "When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information."
  • Following parameters are added in the fPLL IP Core parameters table: "Message level for rule violations", "Enable /1 output clock", "Enable /2 output clock", "Enable /4 output clock", "PLL integer/fractional reference clock frequency" and "Enable mcgb_rst and mcgb_rst_stat ports".
2016.12.21 Initial release