L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.2. CMU_PLL Logical Register Map

Stratix 10 CMU_PLL Register Map Summary

Feature Feature Description
CDR/CMU and PMA Calibration Enables user to optimize CDR/CMU and PMA performance when changing the data rate and reference clock.
Optional Reconfiguration Logic CMU PLL- Capability Enables CMU PLL capabilities to be readable.
Optional Reconfiguration Logic CMU PLL- Control & Status Enables users to read the status of CMU PLL functions and reset the CMU PLL.
Embedded Streamer (CMU PLL)

Enables logic in CMU PLL to store the individual profile information and

perform streaming.

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