L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.5.1.13. Link Equalization for Gen3

Gen3 mode requires TX and RX link equalization because of the datarate, the channel characteristics, receiver design, and process variations. The link equalization process allows the Endpoint and Root Port to adjust the TX and RX setup of each lane to improve signal quality. This process results in Gen3 links with a receiver Bit Error Rate (BER) that is less than 10-12.

For detailed information about the four-stage link equalization procedure for 8.0 GT/s datarate, refer to Section 4.2.3 in the PCI Express Base Specification, Rev 3.0. A new LTSSM state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3 equalization. Phases 2 and 3 of link equalization are optional. Each link must progress through all four phases, even if no adjustments occur. If you skip Phases 2 and 3, you speed up link training at the expense of link BER optimization.

Phase 0

Phase 0 includes the following steps:

  1. The upstream component enters Phase 0 of equalization during Recovery.Rcvrconfig by sending EQ TS2 training sets with starting presets for the downstream component. EQ TS2 training sets may be sent at 2.5 GT/s or 5 GT/s.
  2. The downstream component enters Phase 0 of equalization after exiting Recovery.Speed at 8 GT/s. It receives the starting presets from the training sequences and applies them to its transmitter. At this time, the upstream component has entered Phase 1 and is operating at 8 GT/s.
  3. To move to Phase 1, the receiver must have a BER < 10-4. The receiver should be able to decode enough consecutive training sequences.
  4. To move to Equalization Phase 1, the downstream component must detect training sets with Equalization Control (EC) bits set to 2’b01.

Phase 1

During Phase 1 of the equalization process, the link partners exchange Full Swing (FS) and Low Frequency (LF) information. These values represent the upper and lower bounds for the TX coefficients. The receiver uses this information to calculate and request the next set of transmitter coefficients.

  1. The upstream component moves to EQ Phase 2 when training sets with EC bits set to 2'b01 are captured on all lanes. It also sends EC=2’b10, starting pre-cursor, main cursor, and post-cursor coefficients.
  2. The downstream component moves to EQ Phase 2 after detecting these new training sets.
Use the pipe_g3_txdeemph[17:0] port to select the transmitter de-emphasis. The 18 bits specify the following coefficients:
  • [5:0]: C-1
  • [11:6]: C0
  • [17:12]: C+1

Refer to Preset Mappings to TX De-emphasis for the mapping between presets and TX de-emphasis.

Phase 2 (Optional)

During Phase 2, the Endpoint tunes the TX coefficients of the Root Port. The TS1 Use Preset bit determines whether the Endpoint uses presets for coarse resolution or coefficients for fine resolution.

Note: You cannot perform Phase 2 tuning, when you are using the PHY IP Core for PCI Express (PIPE) as an Endpoint. The PIPE interface does not provide any measurement metric to the Root Port to guide coefficient preset decision making. The Root Port should reflect the existing coefficients and move to the next phase. The default Full Swing (FS) value advertised by the Intel device is 60 and Low Frequency (LF) is 20.

If you are using the PHY IP Core for PCI Express (PIPE) as the Root Port, the Endpoint can tune the Root Port TX coefficients.

The tuning sequence typically includes the following steps:

  1. The Endpoint receives the starting presets from the Phase 2 training sets sent by the Root Port.
  2. The circuitry in the Endpoint receiver determines the BER. It calculates the next set of transmitter coefficients using FS and LF. It also embeds this information in the Training Sets for the Link Partner to apply to its transmitter.
    The Root Port decodes these coefficients and presets, performs legality checks for the three transmitter coefficient rules and applies the settings to its transmitter and also sends them in the Training Sets. The three rules for transmitter coefficients are:
    1. |C-1| <= Floor (FS/4)
    2. |C-1|+C0+|C+1| = FS
    3. C0-|C-1|-|C+1 |>= LF

    Where: C0 is the main cursor (boost), C-1 is the pre-cursor (pre-shoot), and C+1 is the post-cursor (de-emphasis).

  3. This process is repeated until the downstream component's receiver achieves a BER of < 10-12

Phase 3 (Optional)

During this phase, the Root Port tunes the Endpoint’s transmitter. This process is analogous to Phase 2 but operates in the opposite direction.

You cannot perform Phase 3 tuning, when you are using the PHY IP Core for PCI Express (PIPE) as a Root Port.

After Phase 3 tuning is complete, the Root Port moves to Recovery.RcvrLock, sending EC=2’b00, and the final coefficients or preset agreed upon in Phase 2. The Endpoint moves to Recovery.RcvrLock using the final coefficients or preset agreed upon in Phase 3.

Recommendations for Tuning Link

Intel recommends transmitting Preset P8 coefficients for the Intel® Stratix® 10 receiver to recover data successfully.

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