L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.16. Transceiver PHY PCS-to-Core Interface Reference Port Mapping

This section lists the following tables for the PCS-to-Core port interface mappings of all the supported configurations for the Enhanced PCS, Standard PCS, and PCS-Direct configurations when Simplified Data Interface is disabled or unavailable. For the port interface mappings for PCIe Gen1-Gen3, refer to the PCIe Express chapter. Refer to these tables when mapping certain port functions to tx_parallel_data and rx_parallel_data. The Intel® Stratix® 10L-/ H-Tile Transceiver PHY PCS-to-Core interface has a maximum 80-bit width parallel data bus per channel which includes data, control, word marker, PIPE, and PMA and PCS status ports depending on the PCS/datapath enabled and transceiver configurations.

Note: When Simplified Data Interface is enabled, some ports go through the slow shift registers (SSR) or fast shift registers (FSR). Refer to the Asynchronous Data Transfer section for more details about FSR and SSR.
Figure 30. PCS-Core Port Interface

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