L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

4.8. Resetting Transceiver Channels Revision History

Document Version Changes
2024.01.30 Made the following changes:
  • Changed rx_set_lockedtoref to rx_set_locktoref in Resetting the Transceiver in CDR Manual Lock Mode section.
  • Changed rx_set_lockedtodata to rx_set_locktodata in Resetting the Transceiver in CDR Manual Lock Mode section.
  • Corrected repeated rx_analogreset_stat<n-1:0> signal to rx_digitalreset_stat<n-1:0> in figures Transceiver PHY Reset Controller FPGA IP System Diagram and Reset Controller, Transceiver PHY and TX PLL IP Cores Interaction.
2023.02.01 Made the following change:
  • Changed tLTD to trx_digitalreset in Receiver Reset Sequence During Device Operation figure in Resetting the Receiver During Device Operation (Auto Mode) section.
2018.07.06 Made the following changes:
  • Changed "user reset" to "reset."
2018.05.16 Made the following changes:
  • For the Reset Controller System Diagrams, moved the tx_ready and rx_ready signals and added "or Intel IP" to the reset controller.
2018.03.16 Made the following changes:
  • Added Tile Type of Native PHY IP options to "Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP Parameters."
2017.06.06 Made the following change:
  • Added a new section "Using PCS Reset Status Ports".
2016.12.21 Initial release