L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.3.1.3. Resetting the Receiver After Power UP

The FPGA automatically calibrates the PLL at every power-up before entering user-mode. Perform a reset sequence after the device enters the user-mode. Your user coded Reset Controller must comply with the reset sequence below to ensure a reliable transmitter initialization after the initial power-up calibration.

The step numbers in this list correspond to the numbers in the following figure.

  1. Deassert rx_analogreset after a minimum duration of trx_analogreset after the device enters user mode. The CONF_DONE pin is asserted when the device enters user mode.
  2. Wait for rx_analogreset_stat signal from the PHY, to deassert, to ensure that rx_analogreset deasserts successfully.
  3. Wait for rx_is_lockedtodata to assert.
  4. Deassert rx_digitalreset after the rx_is_lockedtodata stays asserted for a minimum duration of tLTD of 5us. If the rx_is_lockedtodata is asserted and toggles, you must wait another additional tLTD duration before deasserting rx_digitalreset.
  5. Wait for rx_digitalreset_stat signal from the PHY, to deassert, to ensure that rx_digitalreset deasserts successfully.
Figure 176. Resetting the Receiver After Power Up

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