L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Document Table of Contents TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine

The Interlaken configuration sets the Enhanced PCS TX and RX FIFOs in Interlaken elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port signals are provided to the FPGA fabric. Connect these signals to the MAC layer as required by the protocol. Based on these FIFO status and control signals, you can implement the multi-lane deskew alignment state machine in the FPGA fabric to control the transceiver RX FIFO block.

Note: You must also implement the soft bonding logic to control the transceiver TX FIFO block.

TX Soft Bonding Flow

The MAC layer logic and TX soft bonding logic control the writing of the Interlaken word to the TX FIFO with tx_fifo_wr_en inputby monitoring the TX FIFO flags tx_fifo_full, tx_fifo_pfull, tx_fifo_empty, tx_fifo_pempty . On the TX FIFO read side, a read enable is controlled by the frame generator. If tx_enh_frame_burst_en is asserted high, the frame generator reads data from the TX FIFO.

A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding. The following figure shows the state of the pre-fill process.

Figure 121. TX Soft Bonding Flow

The following figure shows that after deasserting tx_digitalreset, TX soft bonding logic starts filling the TX FIFO until all lanes are full.

Figure 122. TX FIFO Pre-fill (6-lane Interface)

After the TX FIFO pre-fill stage completes, the transmit lanes synchronize and the MAC layer begins to send valid data to the transceiver’s TX FIFO. You must never allow the TX FIFO to overflow or underflow. If it does, you must reset the transceiver and repeat the TX FIFO pre-fill stage.

For a single lane Interlaken implementation, TX FIFO soft bonding is not required.

The following figure shows the MAC layer sending valid data to the Native PHY after the pre-fill stage. tx_enh_frame_burst_en is asserted, allowing the frame generator to read data from the TX FIFO. The TX MAC layer can now control tx_fifo_wr_en and write data to the TX FIFO based on the FIFO status signals.

Figure 123. MAC Sending Valid Data (6-lane Interface)

RX Multi-lane FIFO Deskew State Machine

Add deskew logic at the receiver side to eliminate the lane-to-lane skew created at the transmitter of the link partner, PCB, medium, and local receiver PMA.

Implement a multi-lane alignment deskew state machine to control the RX FIFO operation based on available RX FIFO status flags and control signals.

Figure 124. State Flow of the RX FIFO Deskew

You must assert rx_fifo_align_clr at least four rx_coreclkin cycles to clear the RX FIFO upon exit from rx_digitalreset. Each lane's rx_fifo_rd_en should remain deasserted before the RX FIFO deskew is completed. After frame lock is achieved (indicated by the assertion of rx_enh_frame_lock; this signal is not shown in the above state flow), data is written into the RX FIFO after the first alignment word (SYNC word) is found on that channel. Accordingly, the RX FIFO partially empty flag (rx_fifo_pempty) of that channel is asserted. The state machine monitors the rx_fifo_pempty and rx_fifo_pfull signals of all channels. If the rx_fifo_pempty signals from all channels deassert before any channels rx_fifo_pfull assert, which implies the SYNC word has been found on all lanes of the link, the MAC layer can start reading from all the RX FIFO by asserting rx_fifo_rd_en simultaneously. Otherwise, if the rx_fifo_pfull signal of any channel asserts high before the rx_fifo_pempty signals deassertion on all channels, the state machine needs to flush the RX FIFO by asserting rx_fifo_align_clr high for 4 cycles and repeating the soft deskew process.

The following figure shows one RX deskew scenario. In this scenario, all of the RX FIFO partially empty lanes are deasserted while the pfull lanes are still deasserted. This indicates the deskew is successful and the FPGA fabric starts reading data from the RX FIFO.

Figure 125. RX FIFO Deskew

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