L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.2. Interacting with the Reconfiguration Interface

Each transceiver channel and PLL contains Avalon® memory-mapped interface reconfiguration. The reconfiguration interface on the channel is shared between the channel's PCS, PMA and Embedded Multi-die Interconnect Bridge (EMIB). The reconfiguration interface provides direct access to the programmable space of each channel and PLL. Communication with the channel and PLL reconfiguration interface requires an Avalon® memory-mapped interface master. You can start dynamic reconfiguration sequence of each channel and PLL concurrently or sequentially, depending on how the Avalon® memory-mapped interface master is connected to Avalon® memory-mapped interface reconfiguration. However, you must check for the internal configuration bus arbitration before performing reconfiguration. Refer to Arbitration for more details about requesting access to and returning control of the internal configuration bus from PreSICE.
Figure 233. Reconfiguration Interface in Intel® Stratix® 10 Transceiver IP Cores

A transmit PLL instance has a maximum of one reconfiguration interface. Unlike PLL instances, a Native PHY IP core instance can specify multiple channels. You can use a dedicated reconfiguration interface for each channel or share a single reconfiguration interface across multiple channels to perform dynamic reconfiguration.

Avalon® memory-mapped interface masters interact with the reconfiguration interface by performing Avalon® memory-mapped interface read and write operations to initiate dynamic reconfiguration of specific transceiver parameters. All read and write operations must comply with Avalon® memory-mapped interface specifications.

Figure 234. Top-Level Signals of the Reconfiguration Interface

User-accessible Avalon® memory-mapped interface reconfiguration and PreSICE Avalon® memory-mapped interface share a single internal configuration bus. This bus is arbitrated to get access to the Avalon® memory-mapped interface of the channel or PLL. Refer to the "Arbitration" section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.

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