L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.5. PCS-Core Interface Parameters

This section defines parameters available in the Native PHY IP core GUI to customize the PCS to core interface. The following table describes the available parameters. Based on the selection of the Transceiver Configuration Rule , if the specified settings violate the protocol standard, the Native PHY IP core Parameter Editor prints error or warning messages.

Table 19.  PCS-Core Interface Parameters
Parameter Range Description
General Interface Options
Enable PCS reset status ports On / Off Enables the optional TX digital reset and RX digital reset release status output ports including:
  • tx_transfer_ready: Status port to indicate when TX channel is ready for data transfer. When TX PCS channels are bonded, only the transfer ready status of the master channel is used.
  • rx_transfer_ready: Status port to indicate when RX channel is ready for data transfer. When RX PCS channels are bonded, only the transfer ready status of the master channel is used.
  • osc_transfer_en: Status port to indicate when internal oscillator clock is ready for data transfer.
  • tx_fifo_ready: Status port to indicate when TX FIFO is ready for data transfer.
  • rx_fifo_ready: Status port to indicate when RX FIFO is ready for data transfer.
  • tx_digitalreset_timeout: Status port to indicate when TX PCS digital reset release has timeout but the TX PCS channel is still not ready for data transfer.
  • rx_digitalreset_timeout: Status port to indicate when RX PCS digital reset release has timeout but the RX PCS channel is still not ready for data transfer.

The PCS reset status ports help you to debug on why the transceiver native phy does not come out of reset. You can use these ports to debug common connectivity issues, such as the tx/rx_coreclkin being undriven, incorrect frequency, or FIFOs not being set properly.

Please refer to the "Debugging with the PCS reset status ports" section for more detail.

TX PCS-Core Interface FIFO
TX Core Interface FIFO Mode

Phase-Compensation

Register

Interlaken

Basic

The TX PCS FIFO is always operating in Phase Compensation mode. The selection range specifies one of the following modes for the TX Core FIFO:
  • Phase Compensation: The TX Core FIFO compensates for the clock phase difference between the read clock tx_clkout and the write clocks tx_coreclkin or tx_clkout.
  • Register: This mode is limited to PCS Direct with interface widths of 40 bits or less. The TX Core FIFO is bypassed. You must connect the write clock tx_coreclkin to the read clock tx_clkout. The tx_parallel_data, tx_control and tx_enh_data_valid are registered at the FIFO output. Assert tx_enh_data_valid port 1'b1 at all times.
  • Interlaken: The TX Core FIFO acts as an elastic buffer. In this mode, there are additional signals to control the data flow into the FIFO. Therefore, the FIFO write clock frequency does not have to be the same as the read clock frequency. You can control writes to the FIFO with tx_fifo_wr_en. By monitoring the FIFO flags, you can avoid the FIFO full and empty conditions. The Interlaken frame generator controls reading of the data from the TX FIFO.
  • Basic: The TX Core FIFO acts as an elastic buffer. This mode allows driving write and read side of FIFO with different clock frequencies. Monitor FIFO flag to control write and read operations. For additional details refer to Enhanced PCS FIFO Operation section.

Refer to the Special TX PCS Reset Release Sequence section to see if you need to implement a special reset release sequence in your top-level code.

TX FIFO partially full threshold 0-31 Specifies the partially full threshold for the PCS TX Core FIFO. Enter the value at which you want the TX Core FIFO to flag a partially full status.
TX FIFO partially empty threshold 0-31 Specifies the partially empty threshold for the PCS TX Core FIFO. Enter the value at which you want the TX Core FIFO to flag a partially empty status.
Enable tx_fifo_full port On / Off Enables the tx_fifo_full port. This signal indicates when the TX Core FIFO is full. This signal is synchronous to tx_coreclkin.
Enable tx_fifo_empty port On / Off Enables the tx_fifo_empty port. This signal indicates when the TX Core FIFO is empty. This is an asynchronous signal.
Enable tx_fifo_pfull port On / Off Enables the tx_fifo_pfull port. This signal indicates when the TX Core FIFO reaches the specified partially full threshold. This signal is synchronous to tx_coreclkin.
Enable tx_fifo_pempty port On / Off Enables the tx_fifo_pempty port. This signal indicates when the Core TX FIFO reaches the specified partially empty threshold. This is an asynchronous signal.
Enable tx_dll_lock port On/Off Enables the transmit delay locked-loop port. This signal is synchronous to tx_clkout.
Enable TX Data Valid Gen manual setting On/Off For Basic (Enhanced PCS) mode this parameter must be set to On for proper gearbox operation.
RX PCS-Core Interface FIFO
RX PCS-Core Interface FIFO Mode

Phase-Compensation

Phase-Compensation - Register

Phase Compensation - Basic

Register

Register - Phase Compensation

Register - Basic

Interlaken

10GBASE-R
Specifies one of the following modes for PCS RX FIFO:
  • Phase Compensation: This mode places both the RX PCS FIFO and RX Core FIFO in Phase Compensation mode. It compensates for the clock phase difference between the read clocks rx_coreclkin or tx_clkout and the write clock rx_clkout.
  • Phase Compensation-Register: This mode places the RX PCS FIFO in Phase Compensation mode and the RX Core FIFO in Register Mode. The RX Core FIFO's read clock rx_coreclkin and write clock rx_clkout are tied together. With double rate transfer mode disabled, this mode is limited to Standard PCS PMA widths combinations of 8, 10, 16, or 20 with byte serializer/deserializer disabled and Enhanced PCS with Gearbox Ratios of 32:32 or 40:40 and PCS Direct with interface widths of 40-bits or less. Additional configurations can be supported with double rate transfer mode enabled.
  • Phase Compensation-Basic: This mode places the RX PCS FIFO in Phase Compensation mode and the RX Core FIFO in Basic Mode. This mode can only be used with Enhanced PCS and PCS Direct. The RX Core FIFO in Basic mode acts as an elastic buffer or clock crossing FIFO similar to Interlaken mode where the rx_coreclkin and rx_clkout can be asynchronous and of different frequencies. You must implement a FSM that monitors the FIFO status flags and manage the FIFO read and write enable in preventing the FIFO overflow and underflow conditions.
  • Register : This mode is limited to PCS Direct with interface widths of 40 bits or less. The RX PCS FIFO and RX Core FIFO is bypassed. The FIFO's read clock rx_coreclkin and write clock rx_clkout are tied together. The rx_parallel_data, rx_control, and rx_enh_data_valid are registered at the FIFO output.
  • Register-Phase Compensation: This mode places the RX PCS FIFO in Register mode and the RX Core FIFO in Phase Compensation mode. This mode is limited to Standard PCS PMA widths combinations of 8, 10, 16, or 20 with byte serializer/deserializer disabled and Enhanced PCS with Gearbox Ratios of 32:32 or 40:40 and PCS Direct with interface widths of 40-bits or less.
  • Register-Basic: This mode places the RX PCS FIFO in Register mode and the RX Core FIFO in Basic mode. This mode can only be used with Enhanced PCS with Gearbox Ratios of 32:32 or 40:40 and PCS Direct with interface widths of 40-bits or less. The RX Core FIFO in Basic mode acts as an elastic buffer or clock crossing FIFO similar to Interlaken mode where the rx_coreclkin and rx_clkout can be asynchronous and of different frequencies. You must implement a FSM that monitors the FIFO status flags and manage the FIFO read and write enable in preventing the FIFO overflow and underflow conditions.
  • Interlaken: Select this mode for the Interlaken protocol. To implement the deskew process, you must implement an FSM that controls the FIFO operation based on FIFO flags. In this mode the FIFO acts as an elastic buffer.
  • 10GBASE-R: In this mode, data passes through the FIFO after block lock is achieved. OS (Ordered Sets) are deleted and Idles are inserted to compensate for the clock difference between the RX PMA clock and the fabric clock of +/- 100 ppm for a maximum packet length of 64000 bytes.
Note: The fifo status flags are for Interlaken and Basic mode only. They should be ignored in all other cases.
RX FIFO partially full threshold 0-63 Specifies the partially full threshold for the PCS RX Core FIFO. The default value is 5.
RX FIFO partially empty threshold 0-63 Specifies the partially empty threshold for the PCS RX Core FIFO. The default value is 2.
Enable RX FIFO alignment word deletion (Interlaken) On / Off When you turn on this option, all alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion.
Enable RX FIFO control word deletion (Interlaken) On / Off When you turn on this option, Interlaken control word removal is enabled. When the Enhanced PCS RX Core FIFO is configured in Interlaken mode, enabling this option, removes all control words after frame synchronization is achieved. Enabling this option requires that you also enable alignment word deletion.
Enable rx_data_valid port On / Off Enables the rx_data_valid port. When asserted, this signal indicates when there is valid data on the RX parallel databus.
Enable rx_fifo_full port On / Off Enables the rx_fifo_full port. This signal is required when the RX Core FIFO is operating in Interlaken or Basic mode and indicates when the RX Core FIFO is full. This is an asynchronous signal.
Enable rx_fifo_empty port On / Off Enables the rx_fifo_empty port. This signal indicates when the RX Core FIFO is empty. This signal is synchronous to rx_coreclkin.
Enable rx_fifo_pfull port On / Off Enables the rx_fifo_pfull port. This signal indicates when the RX Core FIFO has reached the specified partially full threshold that is set through the Native PHY IP core PCS-Core Interface tab. This is an asynchronous signal.
Enable rx_fifo_pempty port On / Off Enables the rx_fifo_pempty port. This signal indicates when the RX Core FIFO has reached the specified partially empty threshold that is set through the Native PHY IP core PCS-Core Interface tab. This signal is synchronous to rx_coreclkin.
Enable rx_fifo_del port (10GBASE‑R) On / Off Enables the optional rx_fifo_del status output port. This signal indicates when a word has been deleted from the RX Core FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This is an asynchronous signal.
Enable rx_fifo_insert port (10GBASE‑R) On / Off Enables the rx_fifo_insert port. This signal indicates when a word has been inserted into the Core FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This signal is synchronous to rx_coreclkin.
Enable rx_fifo_rd_en port On / Off Enables the rx_fifo_rd_en input port. This signal is enabled to read a word from the RX Core FIFO. This signal is synchronous to rx_coreclkin and is required when the RX Core FIFO is operating in Interlaken or Basic mode.
Enable rx_fifo_align_clr port (Interlaken) On / Off Enables the rx_fifo_align_clr input port. Only used for Interlaken. This signal is synchronous to rx_clkout.
Table 20.  TX Clock Options
Parameter Range Description
Selected tx_clkout clock source

PCS clkout

PCS clkout x2

pma_div_clkout

Specifies the tx_clkout output port source.

Data rate must be equal or higher than 5 Gbps if tx_pma_div_clkout is selected as the clock source for tx_clkout2.

Enable tx_clkout2 port On/ Off Enables the tx_clkout2 port.
Selected tx_clkout2 clock source

PCS clkout

PCS clkout x2

pma_div_clkout

You must enable tx_clkout2 port in order to make a selection for this parameter.

Specifies the tx_clkout2 output port source.

TX pma_div_clkout division factor

Disabled

1, 2, 33, 40, 66

You must select the pma_div_clkout under selected tx_clkout clock source or tx_clkcout2 clock source option in order to enable a selection for this parameter.

Selects the divider that generates the appropriate pma_div_clkout frequency that the tx_clkout or tx_clkout2 ports use.

Example:

For 10.3125 Gbps datarate, if the divider value 33 is selected, the pma_div_clkout resulting frequency is 156.25MHz.

Selected tx_coreclkin clock network

Dedicated Clock

Global Clock

Specifies the clock network used to drive the tx_coreclkin input.

Select “Dedicated Clock” if the tx_coreclkin input port is being driven by either tx/rx_clkout or tx/rx_clkout2 from the transceiver channel.

Select “Global Clock” if the tx_coreclkin input port is being driven by the Fabric clock network. You can also select “Global Clock” if tx_coreclkin is being driven by tx/rx_clkout or tx/rx_clkout2 via the Fabric clock network.

Enable tx_coreclkin2 port On/ Off Enable this clock port to provide a fifo read clock when you have double rate transfer enabled with a PMA width of 20 without byte serialization.
Table 21.  RX Clock Options
Parameter Range Description
Selected rx_clkout clock source

PCS clkout

PCS clkout x2

pma_div_clkout

Specifies the rx_clkout output port source.
Enable rx_clkout2 port On/ Off Enables the rx_clkout2 port.
Selected rx_clkout2 clock source

PCS clkout

PCS clkout x2

pma_div_clkout

You must enable rx_clkout2 port in order to make a selection for this parameter.

Specifies the rx_clkout2 output port source.

RX pma_div_clkout division factor

Disabled

1, 2, 33, 40, 66

You must select the pma_div_clkout under selected rx_clkout clock source or selected rx_clkcout2 clock source option in order to enable a selection for this parameter.

Selects the divider that generates the appropriate pma_div_clkout frequency that the rx_clkout port uses.

Example:

For 10.3125Gbps datarate, if the divider value 33 is selected, the pma_div_clkout resulting frequency is 156.25MHz.

Selected rx_coreclkin clock network

Dedicated Clock

Global Clock

Specifies the clock network used to drive the rx_coreclkin input.

Select “Dedicated Clock” if the rx_coreclkin input port is being driven by either tx/rx_clkout or tx/rx_clkout2 from the transceiver channel.

Select “Global Clock” if the rx_coreclkin input port is being driven by the Fabric clock network. You can also select “Global Clock” if rx_coreclkin is being driven by tx/rx_clkout or tx/rx_clkout2 via the Fabric clock network.

Table 22.  Latency Measurements Options
Parameter Range Description
Enable latency measurement ports On/ Off

Enables latency measurement ports:

tx_fifo_latency_pulse, rx_fifo_latency_pulse

tx_pcs_fifo_latency_pulse, rx_pcs_fifo_latency_pulse, latency_sclk

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