L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3. PLLs and Clock Networks

This chapter describes the transceiver phase locked loops (PLLs), internal clocking architecture, and the clocking options for the transceiver and the FPGA fabric interface.

Transceiver banks have six transceiver channels. There are two advanced transmit (ATX) PLLs, two fractional PLLs (fPLL), two CMU PLLs, and two Master clock generation blocks (CGB) in each bank.

The Intel® Stratix® 10 transceiver clocking architecture supports both bonded and non-bonded transceiver channel configurations. Channel bonding is used to minimize the clock skew between multiple transceiver channels. For Intel® Stratix® 10 transceivers, the term bonding can refer to PMA bonding as well as PMA and PCS bonding. For more details, refer to the Channel Bonding section.

Figure 137.  Intel® Stratix® 10 PLLs and Clock Networks

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