L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.1.2.3. fPLL IP Core - Parameters, Settings, and Ports

Table 131.  fPLL IP Core - Configuration Options, Parameters, and Settings
Parameters Range Description

fPLL Mode

Core

Cascade Source

Transceiver

Specifies the fPLL mode of operation.

Select Core to use fPLL as a general purpose PLL to drive the FPGA core clock network. fPLL in Core mode does not support the dynamic reconfiguration feature.

Select Cascade Source to connect an fPLL to another PLL as a cascading source.

Select Transceiver to use an fPLL as a transmit PLL for the transceiver block.

Message level for rule violations

Error/Warning

Sets rule checking level

Selecting "error" causes all rule violations to prevent IP generation.

Selecting "warning" displays all rule violations as warnings and allows IP generation in spite of violations.

Protocol Mode

Basic

PCIe Gen1

PCIe Gen2

PCIe Gen3

SDI_cascade

OTN_cascade

SATA GEN3

HDMI

Governs the internal setting rules for the VCO.

This parameter is not a preset. You must set all parameters for your protocol.

Bandwidth

Low

Medium

High

Specifies the VCO bandwidth.

Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.

Number of PLL reference clocks

1 to 5

Specify the number of input reference clocks for the fPLL.

Selected reference clock source

0 to 4

Specifies the initially selected reference clock input to the fPLL.

Enable fractional mode

On/Off

Enables the fractional frequency mode.

This enables the PLL to output frequencies which are not integral multiples of the input reference clock.

VCCR_GXB and VCCT_GXB supply voltage for the Transceiver

1_0V, and 1_1V 46

Specifies the Transceiver supply voltage.

PLL output frequency

User defined

Displays the target output frequency for the PLL.

PLL output datarate

Read-only

Displays the PLL datarate.

PLL integer reference clock frequency

User defined

Set the fPLL's reference clock frequency for clock synthesis.

Configure counters manually

On/Off

Selecting this option allows you to manually specify M, N, C and L counter values.

Multiply factor (M-counter)

8 to 127 (integer mode)

11 to 123 (fractional mode)

Specifies the multiply factor (M-counter).

Divide factor (N-counter)

1 to 31

Specifies the divide factor (N-counter).

Divide factor (L-counter)

1, 2, 4, 8

Specifies the divide factor (L-counter).

Divide factor (C-counter)

1 to 512

Specifies the fPLL output clock frequency to the core when configured in core mode.

Table 132.  fPLL—Master Clock Generation Block Parameters and Settings
Parameters Range Description

Include Master Clock Generation Block

On/Off

When enabled, includes a master CGB as a part of the fPLL IP core. The PLL output drives the master CGB.

This is used for x6/x24 bonded and non-bonded modes.

Clock division factor

1, 2, 4, 8

Divides the master CGB clock input before generating bonding clocks.

Enable x24 non-bonded high-speed clock output port

On/Off

Enables the master CGB serial clock output port used for x6/xN non-bonded modes.

Enable PCIe clock switch interface

On/Off

Enables the control signals used for PCIe clock switch circuitry.

Enable mcgb_rst and mcgb_rst_stat ports

On/Off

The mcgb_rst and mcgb_rst_stat ports are required when the transceivers are configured in PCIE Gen 3 x2/x4/x8/x16 PIPE mode

.

Number of auxiliary MCGB clock input ports

0-1

The number should be set to 1 when the transceivers are configured in PCIE Gen 3 x2/x4/x8/x16 PIPE mode and 0 for all other modes.

MCGB input clock frequency

Read only

Displays the master CGB’s required input clock frequency. You cannot set this parameter.

MCGB output data rate

Read only

Displays the master CGB’s output data rate. You cannot set this parameter.

This value is calculated based on MCGB input clock frequency and MCGB clock division factor.

Enable bonding clock output ports

On/Off

Enables the tx_bonding_clocks output ports of the Master CGB used for channel bonding.

You must enable this parameter for bonded designs.

PMA interface width

8, 10, 16, 20, 32, 40, 64

Specifies the PMA-PCS interface width.

Match this value with the PMA interface width selected for the Native PHY IP core. You must select a proper value for generating bonding clocks for the Native PHY IP core.

Table 133.  fPLL IP Core - Dynamic Reconfiguration
Parameters Range Description

Enable dynamic reconfiguration

On/Off

Enables the dynamic reconfiguration interface.

Enable Native PHY Debug Master Endpoint

On/Off

When enabled, the PLL IP includes an embedded Native PHY Debug Master Endpoint that connects internally Avalon® memory-mapped interface slave. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the "Share reconfiguration interface" option for configurations using more than 1 channel and may also require that a jtag_debug link be included in the system.

Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE

On/Off

When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.

Enable capability registers

On/Off

Enables capability registers, which provide high level information about the transceiver PLL's configuration

Set user-defined IP identifier

1 to 5

Sets a user-defined numeric identifier that can be read from the user_identifer offset when the capability registers are enabled

Enable control and status registers

On/Off

Enables soft registers for reading status signals and writing control signals on the phy interface through the embedded debug. Available signals include pll_cal_busy, pll_locked and pll_powerdown.

Configuration file prefix

On/Off

Specifies the file prefix to use for generated configuration files when enabled. Each variant of the IP should use a unique prefix for configuration files.

Generate SystemVerilog package file

On/Off

When enabled, The IP generates a SystemVerilog package file named "(Configuration file prefix)_reconfig_parameters.sv" containing parameters defined with the attribute values needed for reconfiguration.

Generate C header file

On/Off

When enabled, The IP generates a C header file named "(Configuration file prefix)_reconfig_parameters.h" containing macros defined with the attribute values needed for reconfiguration.

Generate MIF (Memory Initialize File)

On/Off

When enabled The IP generates an MIF (Memory Initialization File) named "(Configuration file prefix)_reconfig_parameters.mif". The MIF file contains the attribute values needed for reconfiguration in a data format.

Enable multiple reconfiguration profiles

On/Off

When enabled, you can use the GUI to store multiple configurations. The IP generates reconfiguration files for all of the stored profiles. The IP also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them.

Enable embedded reconfiguration streamer

On/Off

Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles.

Generate reduced reconfiguration files

On/Off

When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles.

Number of reconfiguration profiles

1 to 31

Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.

Store current configuration to profile:

1, 2, 4, 8

Selects which reconfiguration profile to store when clicking the "Store profile" button.

Table 134.  fPLL IP Core - Ports
Port Direction Clock Domain Description
pll_refclk0

Input

N/A

Reference clock input port 0.

There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.

pll_refclk1

Input

N/A

Reference clock input port 1.

pll_refclk2

Input

N/A

Reference clock input port 2.

pll_refclk3

Input

N/A

Reference clock input port 3.

pll_refclk4

Input

N/A

Reference clock input port 4.

mcgb_aux_clk0

Input

N/A

Used for PCIe to switch between fPLL/ATX PLL during link speed negotiation.

pcie_sw[1:0]

Input

Asynchronous

2-bit rate switch control input used for PCIe protocol implementation.

mcgb_rst

Input

N/A

Resets the master CGB. This port should be used when implementing PCI Express Gen 3 PIPE only.

tx_serial_clk

Output

N/A

High speed serial clock output port for GX channels. Represents the x1 clock network.

pll_locked

Output

Asynchronous

Active high status signal which indicates if PLL is locked.

pll_cascade_clk

Output N/A fPLL cascade clock output port

pll_pcie_clk

Output

N/A

Used for PCIe.

pll_cal_busy

Output

Asynchronous

Status signal which is asserted high when PLL calibration is in progress.

Perform logical OR with this signal and the tx_cal_busy port on the reset controller IP.

tx_bonding_clocks[5:0]

Output

N/A

Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB.

Used for channel bonding, and represents the x6/x24 clock network.

mcgb_serial_clk

Output

N/A

High speed serial clock output for x6/x24 non-bonded configurations.

pcie_sw_done[1:0]

Output

Asynchronous

2-bit rate switch status output used for PCIe protocol implementation.

pll_cascade_clk

Output

N/A

fPLL cascade output port
outclk_div1

Output

N/A

Core output clock (only in Core mode). The frequency is the PLL output frequency. No phase relationship to refclk.

outclk_div2

Output

N/A

Core output clock (only in Core mode). The frequency is half of the outclk_div1 frequency. Phase aligned to outclk_div1.

outclk_div4

Output

N/A

Core output clock (only in Core mode). The frequency is quarter of the outclk_div1 frequency. Phase aligned to outclk_div1.

mcgb_rst_stat

Output

N/A

Status signal for the master CGB. This port should be used when implementing PCI Express Gen 3 PIPE only
46 Refer to the Intel® Stratix® 10Device Datasheet for details about the minimum, typical, and maximum supply voltage specifications.

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