L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Public
Document Table of Contents

4.3.1.5.2. Resetting the Transceiver in CDR Manual Lock Mode

The numbers in this list correspond to the numbers in the following figure, which guides you through the steps to put the CDR in manual lock mode.

  1. Make sure that the calibration is complete (rx_cal_busy is low) and the transceiver goes through the initial reset sequence. The rx_digitalreset and rx_analogreset signals should be low. The rx_is_lockedtoref is a don't care and can be either high or low. The rx_is_lockedtodata and rx_ready signals should be high, indicating that the transceiver is out of reset. Alternatively, you can start directly with the CDR in manual lock mode after the calibration is complete.
  2. Assert the rx_set_locktoref signal high to switch the CDR to the lock-to-reference mode. The rx_is_lockedtodata status signal is deasserted. Assert the rx_digitalreset signal high at the same time or after rx_set_locktoref is asserted if you use the user-coded reset. When the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP is used in auto reset mode, the rx_digitalreset is automatically asserted. When the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP is used in manual reset mode, the rx_digitalreset must be manually asserted after the assertion of rx_set_locktoref.
    1. Wait for rx_digitalreset_stat to assert, to ensure that rx_digitalreset asserts successfully in the PCS.
  3. After the rx_digitalreset_stat signal gets asserted, the rx_ready status signal is deasserted.
  4. Assert the rx_set_locktodata signal high tLTR_LTD_Manual (minimum 15 µs) after the CDR is locked to reference i.e. rx_is_lockedtoref should be high and stable for a minimum tLTR_LTD_Manual (15 µs), before asserting rx_set_locktodata. This is required to filter spurious glitches on rx_is_lockedtoref. The rx_is_lockedtodata status signal gets asserted, which indicates that the CDR is now set to LTD mode. The rx_is_lockedtoref status signal can be a high or low and can be ignored after asserting rx_set_locktodata high after the CDR is locked to reference.
  5. Deassert the rx_digitalreset signal after a minimum of tLTD_Manual.
    1. Wait for rx_digitalreset_stat to deassert, to ensure that rx_digitalreset deasserts successfully in the PCS
  6. If you are using the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP, the rx_ready status signal gets asserted after the rx_digitalreset signal is deasserted. This indicates that the receiver is now ready to receive data with the CDR in manual mode.
Figure 178. Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode