L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

1.3.6.1. 100G Ethernet MAC Hard IP

The 100G Ethernet MAC Hard IP block implements an Ethernet stack with MAC and PCS layers, as defined in the www.ieee802.org/3/.
Note: This Hard IP only apples to Intel® Stratix® 10 H-Tile devices.
  • Supported Protocols
    • 100G MAC + PCS Ethernet x4 lanes
  • Modes
    • MAC + PCS
    • PCS only
    • PCS66 (encoder/scrambler bypass)
    • Loopbacks
    • AN/LT with soft logic: dynamic switching
  • Requires a soft Auto Negotiation / Link Training (AN/LT) logic implemented in the core fabric. Implement the AN/LT logic, or use a MAC IP.
Note:

Auto negotiation (AN) is an exchange in which link partners to determine the highest performance datarate that they both support. Link training (LT) is the process that defines how a receiver (RX) and a transmitter (TX) on a high-speed serial link communicate with each other to tune their PMA settings.

The protocol specifies how to request the link partner TX driver to adjust TX deemphasis, but the standard does not state how or when to adjust receiver equalization. The manufacturer determines how they adjust their receiver equalization. The algorithm for RX settings is different between tiles.

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