L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.11.2. Transceiver to FPGA Fabric Transfer

For signals that are going out from the transceiver to the FPGA Fabric, there is update logic in the transceiver that updates the signal level of the interface ports following the shift register update cycle.

There are minimum frequency requirements for FSR and SSR signals as listed below. You must capture the signals using a clock that is ≥ the frequency in the table below.

Table 89.  Register Chain Minimum Sampling Frequency
Register Chain Minimum Sampling Frequency (Without Using the Hard IP) 22 Minimum Sampling Frequency (Using the Hard IP) 22
FSR 225 MHz 113 MHz
SSR 10.98 MHz 10 MHz

Given that the internal oscillator clock frequency can vary between 600 MHz and 900 MHz in the hardware, use a sampling frequency for the worst case scenario of 900 MHz as summarized above.

22 The calculation assumes an OSC divider factor of 1.

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