184.108.40.206.2. Transceiver to FPGA Fabric Transfer
There are minimum frequency requirements for FSR and SSR signals as listed below. You must capture the signals using a clock that is ≥ the frequency in the table below.
|Register Chain||Minimum Sampling Frequency (Without Using the Hard IP) 22||Minimum Sampling Frequency (Using the Hard IP) 22|
|FSR||225 MHz||113 MHz|
|SSR||10.98 MHz||10 MHz|
Given that the internal oscillator clock frequency can vary between 600 MHz and 900 MHz in the hardware, use a sampling frequency for the worst case scenario of 900 MHz as summarized above.
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