L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.7.2. RX Data Bitslip

When using the Enhanced PCS, the RX data bitslip in the RX gearbox allows you to slip the recovered data.

An asynchronous active high edge on the rx_bitslip port changes the word boundary, shifting rx_parallel_data one bit at a time. Use the rx_bitslip port with its own word aligning logic. Assert the rx_bitslip signal for at least two parallel clock cycles to allow synchronization. You can verify the word alignment by monitoring rx_parallel_data. Using the RX data bitslip feature is optional.

Figure 72. RX Bitslip

Refer to the RX Gearbox, RX Bitslip, and Polarity Inversion section for more information.

To use the RX bitslip feature when using the Standard PCS, select Enable rx_bitslip port and set the word aligner mode to bitslip. This adds rx_bitslip as an input control port. An active high edge on rx_bitslip slips one bit at a time. When rx_bitslip is switched between high and low, the word aligner slips one bit at a time on every active high edge. Assert the rx_bitslip signal for at least two parallel clock cycles to allow synchronization. You can verify this feature by monitoring rx_parallel_data.

Figure 73. RX Bitslip in 8-bit Mode tx_parallel_data = 8'hbc
Figure 74. RX Bitslip in 10-bit Mode tx_parallel_data = 10'h3bc
Figure 75. RX Bitslip in 16-bit Mode tx_parallel_data = 16'hfcbc
Figure 76. RX Bitslip in 20-bit Mode tx_parallel_data = 20'h3fcbc

Refer to the Word Aligner Bitslip Mode section for more information.

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