18.104.22.168.2. RX Data Bitslip
An asynchronous active high edge on the rx_bitslip port changes the word boundary, shifting rx_parallel_data one bit at a time. Use the rx_bitslip port with its own word aligning logic. Assert the rx_bitslip signal for at least two parallel clock cycles to allow synchronization. You can verify the word alignment by monitoring rx_parallel_data. Using the RX data bitslip feature is optional.
Refer to the RX Gearbox, RX Bitslip, and Polarity Inversion section for more information.
To use the RX bitslip feature when using the Standard PCS, select Enable rx_bitslip port and set the word aligner mode to bitslip. This adds rx_bitslip as an input control port. An active high edge on rx_bitslip slips one bit at a time. When rx_bitslip is switched between high and low, the word aligner slips one bit at a time on every active high edge. Assert the rx_bitslip signal for at least two parallel clock cycles to allow synchronization. You can verify this feature by monitoring rx_parallel_data.
Refer to the Word Aligner Bitslip Mode section for more information.