L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.4.1. 8B/10B TX Disparity Control

The Disparity Control feature controls the running disparity of the output from the 8B/10B Decoder.

To enable TX Disparity Control, select the Enable TX 8B/10B Disparity Control option. The following ports are added:
  • tx_forcedisp—a control signal that indicates whether a disparity value has to be forced or not
  • tx_dispval—a signal that indicates the value of the running disparity that is being forced
When the number of data channels is more than 1, tx_forcedisp and tx_dispval are shown as buses in which each bit corresponds to one channel.

The following figure shows the current running disparity being altered in Basic single-width mode by forcing a positive disparity /K28.5/ when it was supposed to be a negative disparity /K28.5/. In this example, a series of /K28.5/ code groups are continuously being sent. The stream alternates between a positive running disparity (RD+) /K28.5/ and a negative running disparity (RD-) /K28.5/ to maintain a neutral overall disparity. The current running disparity at time n + 3 indicates that the /K28.5/ in time n + 4 should be encoded with a negative disparity. Because tx_forcedisp is high at time n + 4, and tx_dispval is low, the /K28.5/ at time n + 4 is encoded as a positive disparity code group.

Figure 63. 8B/10B TX Disparity Control

Refer to the 8B/10B Encoder Current Running Disparity Control Feature section for more information about the 8B/10B data current running disparity control.

Refer to the 8B/10B Decoder Running Disparity Checker Feature section for more information about the 8B/10B data current running disparity checker.

The Interlaken disparity generator and checker blocks of the Enhanced PCS support these functions. Refer to the Interlaken Disparity Generator and Interlaken Disparity Checker sections for more information about the Interlaken disparity generator and checker, respectively.

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