L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Public
Document Table of Contents

6.11. Ports and Parameters

The reconfiguration interface is integrated in the Native PHY instance and the TX PLL instances. Instantiate the Native PHY and the TX PLL IP cores in Qsys by clicking Tools > IP Catalog. You can define parameters for IP cores by using the IP core-specific parameter editor. To expose the reconfiguration interface ports, select the Enable dynamic reconfiguration option when parameterizing the IP core.

You can share the reconfiguration interface among all the channels by turning on Share reconfiguration interface when parameterizing the IP core. When this option is enabled, the IP core presents a single reconfiguration interface for dynamic reconfiguration of all channels. Address bits [10:0] provide the register address in the reconfiguration space of the selected channel. The remaining address bits of the reconfiguration address specify the selected logical channel. For example, if there are four channels in the Native PHY IP instance, reconfig_address[10:0] specifies the address and reconfig_address[12:11] are binary encoded to specify the four channels. For example, 2'b01 in reconfig_address[12:11] specifies logical channel 1.

The following figure shows the signals available when the Native PHY IP core is configured for four channels and the Share reconfiguration interface option is enabled.

Figure 242. Signals Available with Shared Native PHY Reconfiguration Interface
Table 164.  Reconfiguration Interface Ports with Shared Native PHY Reconfiguration InterfaceThe reconfiguration interface ports when Share reconfiguration interface is enabled. <N> represents the number of channels.
Port Name Direction Clock Domain Description
reconfig_clk Input N/A Avalon® clock. The clock frequency is up to 150 MHz.
reconfig_reset Input reconfig_clk Resets the Avalon® interface. Asynchronous assertion and synchronous deassertion.
reconfig_write Input reconfig_clk Write enable signal. Signal is active high.
reconfig_read Input reconfig_clk Read enable signal. Signal is active high.
reconfig_address[log2<N>+10:0] Input reconfig_clk Address bus. The lower 11 bits specify address and the upper bits specify the channel.
reconfig_writedata[31:0] Input reconfig_clk A 32-bit data write bus. Data to be written into the address indicated by reconfig_address.
reconfig_readdata[31:0] Output reconfig_clk A 32-bit data read bus. Valid data is placed on this bus after a read operation. Signal is valid after reconfig_waitrequest goes high and then low.
reconfig_waitrequest Output reconfig_clk A one-bit signal that indicates the Avalon® interface is busy. Keep the Avalon® command asserted until the interface is ready to proceed with the read/write transfer. The behavior of this signal depends on whether the feature Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. For more details, refer to the Calibration section.

When Share reconfiguration interface is off, the Native PHY IP core provides an independent reconfiguration interface for each channel. For example, when a reconfiguration interface is not shared for a four-channel Native PHY IP instance, reconfig_address[10:0] corresponds to the reconfiguration address bus of logical channel 0, reconfig_address[21:11] correspond to the reconfiguration address bus of logical channel 1, reconfig_address[32:22] corresponds to the reconfiguration address bus of logical channel 2, and reconfig_address[43:33] correspond to the reconfiguration address bus of logical channel 3.

The following figure shows the signals available when the Native PHY is configured for four channels and the Share reconfiguration interface option is not enabled.

Figure 243. Signals Available with Independent Native PHY Reconfiguration Interfaces
Table 165.  Reconfiguration Interface Ports with Independent Native PHY Reconfiguration InterfacesThe reconfiguration interface ports when Share reconfiguration interface is disabled. <N> represents the number of channels.
Port Name Direction Clock Domain Description
reconfig_clk[N-1:0] Input N/A Avalon® clock for each channel. The clock frequency is up to 150 MHz.
reconfig_reset[N-1:0] Input reconfig_clk Resets the Avalon® interface for each channel. Asynchronous to assertion and synchronous to deassertion.
reconfig_write[N-1:0] Input reconfig_clk Write enable signal for each channel. Signal is active high.
reconfig_read[N-1:0] Input reconfig_clk Read enable signal for each channel. Signal is active high.
reconfig_address[N*11-1:0] Input reconfig_clk A 11-bit address bus for each channel.
reconfig_writedata[N*32-1:0] Input reconfig_clk A 32-bit data write bus for each channel. Data to be written into the address indicated by the corresponding address field in reconfig_address.
reconfig_readdata[N*32-1:0] Output reconfig_clk A 32-bit data read bus for each channel. Valid data is placed on this bus after a read operation. Signal is valid after waitrequest goes high and then low.
reconfig_waitrequest[N-1:0] Output reconfig_clk A one-bit signal for each channel that indicates the Avalon® interface is busy. Keep the Avalon® command asserted until the interface is ready to proceed with the read/write transfer. The behavior of this signal depends on whether the feature Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. For more details, refer to the Calibration section.
Table 166.   Avalon® Interface ParametersThe following parameters are available in the Dynamic Reconfiguration tab of the Transceiver Native PHY and TX PLL parameter editors.
Parameter Value Description
Enable dynamic reconfiguration On / Off Available in Native PHY and TX PLL IP parameter editors. Enables the reconfiguration interface. Off by default. The reconfiguration interface is exposed when this option is enabled.
Share reconfiguration interface On / Off Available in Native PHY IP parameter editor only. Enables you to use a single reconfiguration interface to control all channels. Off by default. If enabled, the uppermost bits of reconfig_address identifies the active channel. The lower 11 bits specify the reconfiguration address. Binary encoding is used to identify the active channel (available only for Transceiver Native PHY). Enable this option if the Native PHY is configured with more than one channel.
Enable Native PHY Debug Master Endpoint On / Off Available in Native PHY and TX PLL IP parameter editors. When enabled, the Native PHY Debug Master Endpoint (NPDME) is instantiated and has access to the Avalon® memory-mapped interface of the Native PHY. You can access certain test and debug functions using System Console with the NPDME. Refer to the Embedded Debug Features section for more details about NPDME.
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE On / Off When enabled, reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the Enable control and status registers feature under Optional Reconfiguration Logic be enabled. Refer to Arbitration for more details on this feature. Refer to the Calibration chapter for more details about calibration.
Enable rcfg_tx_digitalreset_release_ctrl port On / Off Available in Native PHY IP parameter editor only. Enables the rcfg_tx_digitalreset_release_ctrl port that dynamically controls the TX PCS reset release sequence. This port is mandatory when reconfiguring to/from TX PCS Gearbox ratio of *:67. Deassert this signal at least 30 ns before deasserting tx_digitalreset when the TX PCS Gearbox ratio is configured to *:67. In other modes, assert this signal at least 30 ns before deasserting tx_digitalreset.
Enable capability registers On / Off Available in Native PHY and TX PLL IP parameter editors. Enables capability registers. These registers provide high-level information about the transceiver channel's /PLL's configuration.
Set user-defined IP identifier User-specified Available in Native PHY and TX PLL IP parameter editors. Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Enable control and status registers On / Off Available in Native PHY and TX PLL IP parameter editors. Enables soft registers for reading status signals and writing control signals on the PHY /PLL interface through the NPDME or reconfiguration interface.
Enable PRBS soft accumulators On / Off

Available in Native PHY IP parameter editor only. Enables soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and verifier.

Configuration file prefix User-specified Available in Native PHY and TX PLL IP parameter editors. Specifies the file prefix used for generating configuration files. Use a unique prefix for configuration files for each variant of the Native PHY and PLL.
Generate SystemVerilog package file On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a SystemVerilog package file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.
Generate C header file On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a C header file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.
Generate MIF (Memory Initialize File) On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a MIF file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.
Enable multiple reconfiguration profiles On / Off Available in Native PHY and Transmit PLL IP parameter editors only. Use the Parameter Editor to store multiple configurations. The parameter settings for each profile are tabulated in the Parameter Editor.
Enable embedded reconfiguration streamer On / Off Available in Native PHY and Transmit PLL IP parameter editors only. Embeds the reconfiguration streamer into the Native PHY/Transmit PLL IP cores and automates the dynamic reconfiguration process between multiple predefined configuration profiles.
Generate reduced reconfiguration files On / Off Available in Native PHY and Transmit PLL IP parameter editors only. Enables the Native PHY and Transmit PLL IP cores to generate reconfiguration files that contain only the attributes that differ between multiple profiles.
Number of reconfiguration profiles 1 to 8 Available in Native PHY and Transmit PLL IP parameter editors only. Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Selected reconfiguration profile 0 to 7 Available in Native PHY and Transmit PLL IP parameter editors only. Selects which reconfiguration profile to store when you click Store profile.
Store configuration to selected profile N/A Available in Native PHY and Transmit PLL IP parameter editors only. Stores the current Native PHY and Transmit PLL parameter settings to the profile specified by the Selected reconfiguration profile parameter.
Load configuration from selected profile N/A Available in Native PHY and Transmit PLL IP parameter editors only. Loads the current Native PHY/Transmit PLL IP with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter.
Clear selected profile N/A Available in Native PHY and Transmit PLL IP parameter editors only. Clears the stored Native PHY/Transmit PLL IP parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY/Transmit PLL. In other words, an empty profile reflects the Native PHY/Transmit PLL current parameter settings.
Clear all profiles N/A Available in Native PHY and Transmit PLL IP parameter editors only. Clears the Native PHY/Transmit PLL IP parameter settings for all the profiles.
Refresh selected_profile N/A Available in Native PHY and Transmit PLL IP parameter editors only. Equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the parameter settings from stored profile specified by the Selected reconfiguration profile parameter and then stores the parameters back to the profile.