3.3.5. HCLK Network
In PCIe* mode, the HCLK network drives the PIPE interface by driving pll_pcie_clk from the fPLL or ATX PLL. The HCLK network is separated by a triplet (3 channels in a bank). The three channels in a triplet share the same pll_pcie_clk from either the ATX or fPLL. This means that two independent PCIe* x1 or x2 links cannot be fitted in the same triplet.
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