L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.3.5. HCLK Network

In PCIe* mode, the HCLK network drives the PIPE interface by driving pll_pcie_clk from the fPLL or ATX PLL. The HCLK network is separated by a triplet (3 channels in a bank). The three channels in a triplet share the same pll_pcie_clk from either the ATX or fPLL. This means that two independent PCIe* x1 or x2 links cannot be fitted in the same triplet.

Figure 156. HCLK Network

Did you find the information on this page useful?

Characters remaining:

Feedback Message