L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.2.3. Optional Reconfiguration Logic CMU PLL- Control & Status

Enables users to read the status of CMU PLL functions and reset the CMU PLL.
Name Address Type Attribute Name Encodings
PLL Locked Status

0x480[0]

read-only cmu_pll_locked Indicates if the CMU PLL is locked. 1'b1 indicates the CMU PLL is locked.
PLL Calibration Busy Status

0x480[1]

read-only cmu_cal_busy Indicates the CMU PLL calibration status. 1'b1 indicates the CMU PLL is currently being calibrated.
Avalon® memory-mapped interface Bus Busy Status

0x480[2]

read-only cmu_avmm_busy Shows the status of internal configuration bus arbitration. When set to 1'b1, PreSICE has control of the internal configuration bus. When set to 1'b0, you have control of the internal configuration bus. Refer to the Arbitration section for more details.
PLL Power-down

0x4E0[0]

read-write cmu_pll_powerdown Drives the PLL power-down when the Override is set
Override PLL Power-down

0x4E0[1]

read-write cmu_override_pll_powerdown Ensures the PLL listens to the NPDME pll_powerdown register. 1'b1 indicates the receiver listens to the NPDME pll_powerdown.

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