L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.4.3.4. Other registers needed for PRBS Verifier

Used only in conjunction with the PRBS Verifier feature.
Name Address Type Attribute Name Encodings
Clkslip source select 0x00A[2] read-write clkslip_sel 1'b0: Source is PLD
Datapath mapping mode

0x210[4:0]

read-write datapath_mapping_mode 5'b01001: 10G, 32-bit datapath with 1:1 FIFO
FIFO double write enable

0x214[0]

read-write fifo_double_write 1'b0 = Single width mode
FIFO read clock select

0x322[6:5]

read-write fifo_rd_clk_sel 2'b10: PLD_RX_CLK1 for FIFO read clock
FIFO double width mode

0x312[6]

read-write fifo_double_read 1'b0: Single width mode
Word Marking Bit

0x212[7]

read-write word_mark 1'b0: Disable
RX FIFO Full threshold

0x213[4:0]

read-write rxfifo_full 5'b00111: RX FIFO full threshold
RX FIFO power saving mode

0x218[7:6]

read-write rx_fifo_power_mode 2'b01: Full width, half depth
Phase comp mode read delay

0x213[7:5]

read-write phcomp_rd_del 3'b010: Read delay 2
Adapter Loopback mode

0x218[0]

read-write adapter_lpbk_mode 1'b0: DISABLE
EMIB Loopback mode

0x215[7]

read-write aib_lpbk_mode 1'b0: DISABLE
FIFO write clock select

0x223[1:0]

read-write fifo_wr_clk_sel 2'b00 = FIFO Write Clock Select pld_pcs_rx_clk_out
FIFO write clock select

0x322[4]

read-write fifo_wr_clk_sel 1'b0: Uses rx_transfer_clk for FIFO write clock
FIFO mode

0x315[2:0]

read-write rxfifo_mode 3'b000: Phase compensation
FIFO read allowed or not when empty

0x313[6]

read-write fifo_stop_rd 1'b0: Read when empty
FIFO write allowed or not when full

0x313[7]

read-write fifo_stop_wr 1'b0: Write when full
PLD clk1 delay path sel

0x321[4:1]

read-write pld_clk1_delay_sel 4'b1100: Delay path 12
FIFO Partially empty threshold

0x313[5:0]

read-write rxfifo_pempty 6'b000010: Partially empty threshold = 2
RX FIFO Write control

0x318[1]

read-write rx_fifo_write_ctrl 1'b1: Keep writing when block lock is lost
RX FIFO Power saving mode

0x31A[4:2]

read-write rx_fifo_power_mode 3'b001: Full width, single width mode
Custom pulse stretching amount for PLD async outputs

0x320[2:0]

read-write stretch_num_stages 3'b010: 2 cycle stretch
EMIB clock select

0x322[1:0]

read-write aib_clk1_sel 2'b01: Uses PLD_PCS_RX_CLK_OUT for EMIB clk
Word align

0x318[0]

read-write word_align 1'b0: Disable word align
Loopback mode

0x315[6]

read-write lpbk_mode 1'b0: DISABLE
Data Valid mode

0x312[7]

read-write dv_mode 1'b0: Data valid disable
FIFO empty threshold

0x311[5:0]

read-write rxfifo_empty 6'b000000: RX FIFO empty threshold
FIFO Full threshold

0x312[5:0]

read-write rxfifo_full 6'b000111: FIFO Full threshold
Deserializer EMIB clk x1

0x164[7]

read-write deser_aibck_x1 1'b1: Sends x1 clock out

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