L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

1.3.7. PCIe Gen1/Gen2/Gen3 Hard IP Block

The PCIe Hard IP is an IP block that provides multiple layers of the protocol stack for PCI Express. The Intel® Stratix® 10 Hard IP for PCIe is a complete PCIe solution that includes the Transaction, Data Link, and PHY/MAC layers. The Hard IP solution contains dedicated hard logic that connects to the transceiver PHY interface. Each transceiver tile contains a PCIe Hard IP block supporting PCIe Gen1, Gen2, or Gen3 protocols with x1, x2, x4, x8, and x16 configurations. x1, x2, and x4 configurations result in unusable channels. The Hard IP resides at the bottom of the tile, and is 16 channels high. Additionally, the block includes extensible VF (Virtual Functions) interface to enable implementation of up to 2K VFs via the SRIOV-w (Single-Root I/O Virtualization) bridge. The following table and figure show the possible PCIe Hard IP channel configurations, the number of unusable channels, and the number of channels available for other protocols.

Table 9.  PCIe Hard IP Channel Configurations Per Transceiver Tile
PCIe Hard IP Configuration Number of Unusable Channels Number of Channels Available for Other Protocols
PCIe x1 7 16 (4 for Intel® Stratix® 10 GX 10M devices)
PCIe x2 6 16 (4 for Intel® Stratix® 10 GX 10M devices)
PCIe x4 4 16 (4 for Intel® Stratix® 10 GX 10M devices)
PCIe x8 0 16 (4 for Intel® Stratix® 10 GX 10M devices)
PCIe x16 0 8
Figure 20. PCIe Hard IP Channel Configurations Per Transceiver Tile (for Intel® Stratix® 10 GX 10M Devices)
Figure 21. PCIe Hard IP Channel Configurations Per Transceiver Tile (Except Intel® Stratix® 10 GX 10M Devices)

The table below maps all transceiver channels to PCIe Hard IP channels in available tiles.

Table 10.  PCIe Hard IP Channel Mapping Across all Tiles (for Intel® Stratix® 10 GX 10M Devices)
Tile Channel Sequence PCIe Hard IP Channel Index within I/O Bank Bottom Left Tile Bank Number Top Left Tile Bank Number Bottom Right Tile Bank Number Top Right Tile Bank Number
11 4 1EU10 1MU12 1EU20 1MU22
10 3 1EU10 1MU12 1EU20 1MU22
9 1 1EU10 1MU12 1EU20 1MU22
8 0 1EU10 1MU12 1EU20 1MU22
7 7 1 1DU10 1LU12 1DU20 1LU22
6 6 0 1DU10 1LU12 1DU20 1LU22
5 5 5 1CU10 1KU12 1CU20 1KU22
4 4 4 1CU10 1KU12 1CU20 1KU22
3 3 3 1CU10 1KU12 1CU20 1KU22
2 2 2 1CU10 1KU12 1CU20 1KU22
1 1 1 1CU10 1KU12 1CU20 1KU22
0 0 0 1CU10 1KU12 1CU20 1KU22
Table 11.  PCIe Hard IP Channel Mapping Across all Tiles (Except Intel® Stratix® 10 GX 10M Devices)
Tile Channel Sequence PCIe Hard IP Channel Index within I/O Bank Bottom Left Tile Bank Number Top Left Tile Bank Number Bottom Right Tile Bank Number Top Right Tile Bank Number
23 5 1F 1N 4F 4N
22 4 1F 1N 4F 4N
21 3 1F 1N 4F 4N
20 2 1F 1N 4F 4N
19 1 1F 1N 4F 4N
18 0 1F 1N 4F 4N
17 5 1E 1M 4E 4M
16 4 1E 1M 4E 4M
15 15 3 1E 1M 4E 4M
14 14 2 1E 1M 4E 4M
13 13 1 1E 1M 4E 4M
12 12 0 1E 1M 4E 4M
11 11 5 1D 1L 4D 4L
10 10 4 1D 1L 4D 4L
9 9 3 1D 1L 4D 4L
8 8 2 1D 1L 4D 4L
7 7 1 1D 1L 4D 4L
6 6 0 1D 1L 4D 4L
5 5 5 1C 1K 4C 4K
4 4 4 1C 1K 4C 4K
3 3 3 1C 1K 4C 4K
2 2 2 1C 1K 4C 4K
1 1 1 1C 1K 4C 4K
0 0 0 1C 1K 4C 4K

The PCIe Hard IP block includes extensible VF (Virtual Functions) interface to enable the implementation of up to 2K VFs via the SRIOV-2 (Single-Root I/O Virtualization) bridge.

In network virtualization, single root input/output virtualization or SR-IOV is a network interface that allows the isolation of the PCI Express resources for manageability and performance reasons. A single physical PCI Express is shared on a virtual environment using the SR-IOV specification. The SR-IOV specification offers different virtual functions to different virtual components, such as a network adapter, on a physical server machine.

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