L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents

7.3. Power-up Calibration

After the device is powered up, PreSICE automatically initiates the calibration process during device programming. The time required to complete the calibration process after device power-up can vary by device. All tx/rx/pll_cal_busy signals are high after device power up. These tx/rx/pll_cal_busy signals are de-asserted by PreSICE at the completion of the calibration process. You must ensure that the transceiver reset sequence in your design waits for the calibration to complete before resetting the transceiver PLLs and the transceiver channels.

The PreSICE may still control the internal configuration bus even after power-up calibration is complete. Intel recommends that you wait until all tx/rx/pll_cal_busy signals are low before requesting any access.

All power-up calibration starts from the clock network regulator and voltage regulator calibration for all banks and channels.

For applications using both PCIe* Hard IP and non- PCIe* channels, the power-up calibration sequence is:
  1. Clock network calibration for all tiles.
  2. Voltage regulator calibration for all banks, channels, and PLLs.
  3. Wait for PCIe* reference clocks to toggle.
  4. PCIe* HIP0 calibration (if used).
  5. PCIe* HIP1 calibration (if used).
  6. Calibration of all non- PCIe* Hard IP channels in the calibration sequence.
Note: For successful device configuration and proper power-up calibration for your PCIe* link, you must ensure that the PCIe* reference clock is available and stable during power-up. User recalibration for PCIe* links is not supported.
Figure 252. Power-up Calibration Sequence for PCIe* Hard IP and non- PCIe* Channels