L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Public
Document Table of Contents

2.3.13. PCS-Core Interface Ports

This section defines the PCS-Core interface ports common to the Enhanced PCS, Standard PCS, PCIe Gen3 PCS, and PCS Direct configurations.
Figure 27. PCS-Core Interface Ports
Each transceiver channel's transmit and receive 80-bit parallel data interface active and inactive ports depends on specific configuration parameters such as PMA width, FPGA Fabric width, and whether double rate transfer mode is enabled or disabled. The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals. In the following tables, the variables represent the following parameters:
  • <n>—The number of lanes
  • <d>—The serialization factor
  • <s>— The symbol size
  • <p>—The number of PLLs
Table 55.  TX PCS: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description

tx_parallel_data[<n>80-1:0]

Input

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

TX parallel data inputs from the FPGA fabric to the TX PCS. If you select Enable simplified data interface in the Transceiver Native PHY IP core Parameter Editor, tx_parallel_data includes only the bits required for the configuration you specify.

The data ports that are not active must be set to logical state zero. To determine which ports are active, refer to Transceiver PHY PCS-to-Core Interface Port Mapping section.

unused_tx_parallel_data

Input

tx_clkout Port is enabled, when you enable Enable simplified data interface. Connect all of these bits to 0. When Enable simplified data interface is not set, the unused bits are a part of tx_parallel_data. Refer to Transceiver PHY PCS-to-Core Interface Port Mapping to identify the ports you need to set to logical state zero.
tx_control[<n><3>-1:0] or

tx_control[<n><8>-1:0]

Input

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

The tx_control ports have different functionality depending on the Enhanced PCS transceiver configuration rule selected. When Enable simplified data interface is not set, tx_control is part of tx_parallel_data.

Refer to the Enhanced PCS TX and RX Control Ports section for more details.

Refer to Transceiver PHY PCS-to-Core Interface Port Mapping section for port mappings of tx_control ports based on specific configurations.

tx_word_marking_bit Input Synchronous to the clock driving the write side of the FIFO (tx_coreclkin ortx_clkout)

This port is required if double rate transfer mode is enabled. A logic state of Zero on this port indicates the data on tx_parallel_data bus contains the Lower Significant Word. A logic state of One on this port indicates the data on tx_parallel_data bus contains the Upper Significant Word.

Note that Enable simplified data interface must be disabled for double rate transfer mode to be enabled and therefore, tx_word_marking bit always appears as part of tx_parallel_data.

Refer to Transceiver PHY PCS-to-Core Interface Port Mapping section for port mappings of tx_word_marking_bit.

tx_coreclkin Input Clock

The FPGA fabric clock. Drives the write side of the TX FIFO. For the Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32. Using frequency lower than this range can cause the TX FIFO to underflow and result in data corruption.

tx_coreclkin2 Input Clock Enable this clock port to provide a fifo read clock when you have double rate transfer enabled with a PMA width of 20 without byte serialization.
tx_clkout

Output

Clock

User has the option to select the clock source for this port between PCS clkout, PCS clkout x2, and pma_div_clkout. A valid clock source must be selected based on intended configuration.

PCS clkout is a parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configurations. This clocks the blocks of the TX PCS. The frequency of this clock is equal to the datarate divided by PCS/PMA interface width. PCS clkout x2 is a parallel clock generated at twice the frequency of PCS clkout for double transfer rate mode configurations. The frequency of pma_div_clkout is the divided version of the TX PMA parallel clock.

tx_clkout2 Output Clock

User has the option to select the clock source for this port between PCS clkout, PCS clkout x2, and pma_div_clkout. A valid clock source must be selected based on intended configuration. In some cases, double rate transfer and bonding, for example, you may be required to enable this port for data transfer across the EMIB.

PCS clkout is a parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configurations. This clocks the blocks of the TX PCS. The frequency of this clock is equal to the datarate divided by PCS/PMA interface width. PCS clkout x2 is a parallel clock generated at twice the frequency of PCS clkout for double transfer rate mode configurations. The frequency of pma_div_clkout is the divided version of the TX PMA parallel clock.

Table 56.  RX PCS-Core Interface Ports: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description

rx_parallel_data[<n>80-1:0]

Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

RX parallel data from the RX PCS to the FPGA fabric. If you select, Enable simplified data interface in the Transceiver Native PHY IP GUI, rx_parallel_data includes only the bits required for the configuration you specify. Otherwise, this interface is 80 bits wide.

To determine which ports are active for specific transceiver configurations, refer to Transceiver PHY PCS-to-Core Interface Port Mapping. You can leave the unusual ports floating or not connected.

unused_rx_parallel_data

Output

rx_clkout

This signal specifies the unused data ports when you turn on Enable simplified data interface. When simplified data interface is not set, the unused ports are a part of rx_parallel_data. To determine which ports are active for specific transceiver configurations, refer to Transceiver PHY PCS-to-Core Interface Port Mapping. You can leave the unused data outputs floating or not connected.
rx_control[<n> <8>-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

The rx_control ports have different functionality depending on the Enhanced PCS transceiver configuration rule selected. When Enable simplified data interface is not set, rx_control is part of rx_parallel_data.

Refer to the Enhanced PCS TX and RX Control Ports section for more details.

To determine which ports are active for specific transceiver configurations, refer to Transceiver PHY PCS-to-Core Interface Port Mapping.

rx_word_marking_bit Output Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

This port is required if double rate transfer mode is enabled. A logic state of Zero on this port indicates the data on rx_parallel_data bus contains the Lower Significant Word. A logic state of One on this port indicates the data on rx_parallel_data bus contains the Upper Significant Word.

Note that Enable simplified data interface must be disabled for double rate transfer mode to be enabled and therefore, rx_word_marking bit always appears as part of rx_parallel_data.

Refer to Transceiver PHY PCS-to-Core Interface Port Mapping section for port mappings of rx_word_marking_bit.

rx_coreclkin Input Clock

The FPGA fabric clock. Drives the read side of the RX FIFO. For Interlaken protocol, the frequency of this clock could range from datarate/67 to datarate/32.

rx_clkout

Output

Clock

User has the option to select the clock source for this port between PCS clkout, PCS clkout x2, and pma_div_clkout. A valid clock source must be selected based on intended configuration.

The PCS clkout is the low speed parallel clock recovered by the transceiver RX PMA, that clocks the blocks in the RX PCS. The frequency of this clock is equal to datarate divided by PCS/PMA interface width. PCS clkout x2 is a parallel clock generated at twice the frequency of PCS clkout for double transfer rate mode configurations. The frequency of pma_div_clkout is the divided version of the RX PMA parallel clock.

rx_clkout2 Output Clock

User has the option to select the clock source for this port between PCS clkout, PCS clkout x2, and pma_div_clkout. A valid clock source must be selected based on intended configuration.

The PCS clkout is the low speed parallel clock recovered by the transceiver RX PMA, that clocks the blocks in the RX PCS. The frequency of this clock is equal to datarate divided by PCS/PMA interface width. PCS clkout x2 is a parallel clock generated at twice the frequency of PCS clkout for double transfer rate mode configurations. The frequency of pma_div_clkout is the divided version of the RX PMA parallel clock.

Table 57.   TX PCS-Core Interface FIFO
Name Direction Clock Domain Description
tx_fifo_wr_en[<n>-1:0]

Input

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

Assertion of this signal indicates that the TX data is valid. For Basic and Interlaken, you need to control this port based on TX Core FIFO flags so that the FIFO does not underflow or overflow.

Refer to Enhanced PCS FIFO Operation for more details.

tx_enh_data_valid[<n>-1:0]

Input

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

Assertion of this signal indicates that the TX data is valid. For transceiver configuration rules using 10GBASE-R, 10GBASE-R 1588, 10GBASE-R w/KR FEC, 40GBASE-R w/KR FEC, Basic w/KR FEC, or double rate transfer mode, you must control this signal based on the gearbox ratio. You must also use this signal instead of tx_fifo_wr_en whenever the transceiver Enhanced PCS gearbox is not set to a 1:1 ratio such as 66:40 or 64:32 as an example, except in the case of when the RX Core FIFO is configured in Interlaken or Basic mode in which case, you must use tx_fifo_wr_en instead.

Refer to Enhanced PCS FIFO Operation for more details.

tx_fifo_full[<n>-1:0]

Output

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

Assertion of this signal indicates the TX Core FIFO is full. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

tx_fifo_pfull[<n>-1:0]

Output

Synchronous to the clock driving the write side of the FIFO tx_coreclkin or tx_clkout

This signal gets asserted when the TX Core FIFO reaches its partially full threshold that is set through the Native PHY IP core PCS-Core Interface tab. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

tx_fifo_empty[<n>-1:0]

Output

Asynchronous

When asserted, indicates that the TX Core FIFO is empty. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

tx_fifo_pempty[<n>-1:0]

Output

Asynchronous

When asserted, indicates that the TX Core FIFO has reached its specified partially empty threshold that is set through the Native PHY IP core PCS-Core Interface tab. When you turn this option on, the Enhanced PCS enables the tx_fifo_pempty port, which is asynchronous. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

Table 58.  RX PCS-Core Interface FIFO
Name Direction Clock Domain Description
rx_data_valid[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that rx_parallel_data is valid. Discard invalid RX parallel data when rx_data_valid signal is low.

Refer to Enhanced PCS FIFO Operation for more details.

rx_enh_data_valid[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that rx_parallel_data is valid. Discard invalid RX parallel data when rx_enh_data_valid is low. You must use this signal instead of rx_data_valid whenever the transceiver Enhanced PCS gearbox is not set to a 1:1 ratio such as 66:40 or 64:32 as an example, except in the case of when the RX Core FIFO is configured in Interlaken or Basic mode in which case, you must use rx_data_valid instead.

Refer to Enhanced PCS FIFO Operation for more details.

rx_fifo_full[<n>-1:0]

Output

Asynchronous

When asserted, indicates that the RX Core FIFO is full. This signal gets asserted for 2 to 3 clock cycles.Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

rx_fifo_pfull[<n>-1:0]

Output

Asynchronous

When asserted, indicates that the RX Core FIFO has reached its specified partially full threshold. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

rx_fifo_empty[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that the RX Core FIFO is empty. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

rx_fifo_pempty[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that the RX Core FIFO has reached its specified partially empty threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

rx_fifo_del[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that a word has been deleted from the RX Core FIFO. This signal gets asserted for 2 to 3 clock cycles. This signal is used for the 10GBASE-R protocol.

rx_fifo_insert[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that a word has been inserted into the RX Core FIFO. This signal is used for the 10GBASE-R protocol.

rx_fifo_rd_en[<n>-1:0]

Input

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

For RX Core FIFO Interlaken and Basic configurations, when this signal is asserted, a word is read from the RX Core FIFO. You need to control this signal based on RX Core FIFO flags so that the FIFO does not underflow or overflow.
rx_fifo_align_clr[<n>-1:0]

Input

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

FSR 15

When asserted, the RX Core FIFO resets and begins searching for a new alignment pattern. This signal is only valid for the Interlaken protocol. Assert this signal for at least 4 cycles.

Table 59.  Latency Measurement/Adjustment
Name Direction Clock Domain Description
latency_sclk Input clock Latency measurement input reference clock.
tx_fifo_latency_pulse Output tx_coreclkin Latency pulse of TX core FIFO from latency measurement.
tx_pcs_fifo_latency_pulse Output tx_clkout Latency pulse of TX PCS FIFO from latency measurement.
rx_fifo_latency_pulse Output rx_coreclkin Latency pulse of RX core FIFO from latency measurement.
rx_pcs_fifo_latency_pulse; Output rx_clkout Latency pulse of RX PCS FIFO from latency measurement.
15 For a detailed description of FSR and SSR signals, please go to the Asynchronous Data Transfer section.