L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Document Table of Contents Asynchronous Data Transfer

In Intel® Stratix® 10 devices, a list of asynchronous sideband and control signals are transferred between the transceiver and the FPGA Fabric using shift register chains. There are two categories of shift registers

  • Fast shift register (FSR)
  • Slow shift register (SSR)

The FSR has a shorter register chain and is used to transfer signals that are more timing-critical. The SSR has a longer register chain and is used for signals that are less timing-critical.

Refer to the Transceiver PHY PCS-to-Core Interface Reference Port Mapping section for the list of FSR and SSR signals that are transferred using shift register chain

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