L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.2.4. Reference Clock Network

The reference clock network distributes a reference clock source to the entire transceiver tile even if the VCCR_GXB and VCCT_GXB operating voltages of the banks in the tile are different. This allows any reference clock pin to drive any transmitter PLL on the same side of the device. Designs using multiple transmitter PLLs which require the same reference clock frequency and are located in the same tile, can share the same dedicated reference clock (refclk) pin.

In addition, two high quality reference clock line with dedicated voltage regulator are available. In a tile, one line is driven by the bottom reference clocks, and the other line is driven by the top reference clocks. Use the high quality reference clock line for OTN, SDI or GXT implementation.

To assign a reference clock source to a high quality reference clock line, please use the following QSF assignment:

set_instance_assignment -name XCVR_USE_HQ_REFCLK ON -to pin_name

Reference clock and transmitter PLL location awareness is critical when using high quality reference clock lines. For example, there are fitter errors if you use the bottom reference clock in Bank 0 to drive the transmitter PLL in Bank 2 and bottom reference clock in Bank 1 to drive the transmitter PLL in Bank 3.

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