L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents Supported PIPE Features

PIPE Gen1, Gen2, and Gen3 configurations support different features.
Table 98.  Supported Features for PIPE Configurations
Protocol Feature


(2.5 Gbps)


(5 Gbps)


(8 Gbps)

x1, x2, x4, x8, x16 link configurations Yes Yes Yes
PCIe-compliant synchronization state machine Yes Yes Yes
±300 ppm (total 600 ppm) clock rate compensation Yes Yes Yes
Transmitter driver electrical idle Yes Yes Yes
Receiver detection Yes Yes Yes
8B/10B encoding/decoding disparity control Yes Yes No
128b/130b encoding/decoding No No Yes (supported through the Gearbox)
Scrambling/Descrambling No No Yes (implemented in FPGA fabric)
Power state management Yes Yes Yes
Receiver PIPE status encoding pipe_rxstatus[2:0] Yes Yes Yes
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate No Yes No
Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps signaling rate No No Yes
Dynamic transmitter margining for differential output voltage control No Yes Yes
Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB No Yes Yes
Dynamic Gen3 transceiver pre-emphasis, de-emphasis, and equalization No No Yes
PCS PMA interface width (bits) 10 10 32
Receiver Electrical Idle Inference (EII) Implement in FPGA fabric Implement in FPGA fabric Implement in FPGA fabric