L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.7. Simulating the Native PHY IP Core

Use simulation to verify the Native PHY transceiver functionality. The Intel® Quartus® Prime Pro Edition software supports register transfer level (RTL) and gate-level simulation in both ModelSim® Intel® and third-party simulators. You run simulations using your Intel® Quartus® Prime project files.

The following simulation flows are available:

  • Scripting IP Simulation—In this flow you perform the following actions:
    1. Run the ip-setup-simulation utility to generate a single simulation script that compiles simulation files for all the underlying IPs in your design. This script needs to be regenerated whenever you upgrade or modify IPs in the design.
    2. Create a top-level simulation script for compiling your testbench files and simulating the testbench. It sources the script generated in the first action. You do not have to modify this script even if you upgrade or modify the IPs in your design.
  • Custom Flow—This flow allows you to customize simulation for more complex requirements. You can use this flow to compile design files, IP simulation model files, and Intel simulation library models manually.

You can simulate the following netlist:

  • The RTL functional netlist—This netlist provides cycle-accurate simulation using Verilog HDL, SystemVerilog, and VHDL design source code. Intel and third-party EDA vendors provide the simulation models.

Prerequisites to Simulation

Before you can simulate your design, you must have successfully passed Intel® Quartus® Prime Pro Edition Analysis and Synthesis.

Note: When simulating your design, you must apply a power-on reset (two reconfig_clk cycles) to the reconfig_reset signal.

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