L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.1.2. fPLL

The fractional PLL (fPLL) is used for generating clock frequencies for data rates up to 12.5 Gbps. It can support both integer and fractional frequency synthesis. The fPLL can be used as a transmit PLL for transceiver applications. The fPLL can be cascaded from either the ATX or another fPLL, or it can be used to drive the core clock network. There are two fPLLs in each transceiver bank.

PLL cascading enables additional flexibility in terms of reference clock selection.

Figure 146. fPLL Block Diagram

Input Reference Clock

This is the dedicated input reference clock source for the fPLL.

The input reference clock can be driven from one of the following sources. The sources are listed in order of performance, with the first choice giving the best jitter performance.

  • Dedicated reference clock pin
  • Reference clock network
  • Receiver input pin
  • PLL cascade output
  • Core clock network
Note: Each core clock network reference clock pin can only drive fPLLs located on a single tile.

The input reference clock is a differential signal. Intel recommends using the dedicated reference clock pin as the input reference clock source for best jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.

Note: The fPLL calibration is clocked by the OSC_CLK_1 clock, which must be stable and available for the calibration to proceed. Refer to the Calibration section for details about PLL calibration and OSC_CLK_1 clock.

fPLL Reference Clock Multiplexer

The reference clock (refclk) mux selects the reference clock to the PLL from the various available reference clock sources.
Figure 147. Reference Clock Multiplexer

N Counter

The N counter divides the reference clock (refclk) mux's output. The N counter division helps lower the loop bandwidth or reduce the frequency within the phase frequency detector's (PFD) operating range. The N counter supports division factors from 1 to 32.

Phase Frequency Detector

The reference clock (refclk) signal at the output of the N counter block and the feedback clock (fbclk) signal at the output of the M counter block are supplied as inputs to the PFD. The output of the PFD is proportional to the phase difference between the refclk and fbclk inputs. The PFD aligns the fbclk to the refclk. The PFD generates an "Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.

Charge Pump and Loop Filter (CP + LF)

The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency.

Voltage Controlled Oscillator

The fPLL has a ring oscillator based VCO. The VCO uses the following equation to transform the input control voltage into an adjustable frequency clock:

VCO freq = 2 * M * input reference clock/N

N and M are the N counter and M counter division factors.

L Counter

The L counter divides the VCO's clock output. When the fPLL acts as a transmit PLL, the output of the L counter drives the clock generation block (CGB), x1 clock lines and TX PMA.

M Counter

The M counter divides the VCO's clock output. The outputs of the M counter and N counter have same frequency. M counter range is 8 to 127 in integer mode and 11 to 124 in fractional mode.

Lock Detector

The lock detector block indicates when the reference clock and the feedback clock are phase aligned in integer mode, and frequency aligned in fractional mode. The lock detector generates an active high pll_locked signal to indicate that the PLL is locked to its input reference clock.

Delta Sigma Modulator

The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis. In fractional mode, the M value is as follows:

M (integer) + K/2^32, where K is the Fractional multiply factor (K) in the fPLL IP Core Parameter Editor.

The legal values of K are greater than 1% and less than 99% of the full range of 232 and can only be manually entered in the fPLL IP Core Parameter Editor in the Intel® Quartus® Prime Pro Edition.

The output frequency resolution when the fPLL is configured in fractional mode varies with VCO frequency. A 7 GHz VCO frequency results in 1.63 Hz step per K value LSB.

C Counter

The fPLL C counter division factors range from 1 to 512.

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