L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.2. Input Reference Clock Sources

The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.

Intel® Stratix® 10 transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:

  • Dedicated reference clock pins
  • Receiver input pins
  • Reference clock network (with two new high quality reference clock lines)
  • PLL cascade output (fPLL only)
  • Core clock network (fPLL only)
Note: The reference clock sources are distributed to all the banks in the same tile via the reference clock network, even if the banks are at different transceiver voltages. However, the reference clock sources cannot drive across tiles.

Intel recommends using the dedicated reference clock pins and the reference clock network for the best jitter performance.

The following protocols require you to place the reference clock in the same bank as the transmit PLL:

For the best jitter performance, Intel recommends placing the reference clock as close as possible, to the transmit PLL. The following protocols require the reference clock to be placed in same bank as the transmit PLL:
  • OTU2e, OTU2, OC-192 and 10G PON
  • 6G and 12G SDI
Note: For optimum performance of GXT channel, the reference clock of transmit PLL is recommended to be from a dedicated reference clock pin in the same triplet.
Figure 149. Input Reference Clock Sources
Note: In Intel® Stratix® 10 devices, the FPGA fabric core clock network can be used as an input reference source for fPLL only.

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