3.2. Input Reference Clock Sources
The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.
Intel® Stratix® 10 transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:
- Dedicated reference clock pins
- Receiver input pins
- Reference clock network (with two new high quality reference clock lines)
- PLL cascade output (fPLL only)
- Core clock network (fPLL only)
Intel recommends using the dedicated reference clock pins and the reference clock network for the best jitter performance.
The following protocols require you to place the reference clock in the same bank as the transmit PLL:
- OTU2e, OTU2, OC-192 and 10G PON
- 6G and 12G SDI